Computer Engineering Publications Database (2000-2018) Adapting the Cache Line Size to Reduce Off-Chip Memory Traffic 
| Publication Type | Msc Thesis |
|---|---|
| Title | Adapting the Cache Line Size to Reduce Off-Chip Memory Traffic |
| Author(s) | P.J. de Langen |
| Advisor(s) | B.H.H. Juurlink |
| Publication Date | June 2003 |
| CE Thesis Number | CE-MS-2003-12 |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@mastersthesis{,
author = "P.J. de Langen",
title = "Adapting the Cache Line Size to Reduce Off-Chip Memory Traffic",
school = "Delft University of Technology",
address = "Delft, Netherlands",
month = "June",
year = "2003"
}
author = "P.J. de Langen",
title = "Adapting the Cache Line Size to Reduce Off-Chip Memory Traffic",
school = "Delft University of Technology",
address = "Delft, Netherlands",
month = "June",
year = "2003"
}