Computer Engineering Publications Database (2000-2018) Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic 
| Publication Type | Conference Paper |
|---|---|
| Title | Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic |
| Author(s) | P. Celinski S.D. Cotofana D. Abbott |
| Publication Date | May 2003 |
| Conference Name | International Symposium on Circuits and Systems |
| Period | 25-28 May 2003 |
| Location | Bangkok, Thailand |
| ISBN | t.b.s. |
| Page Numbers | 233-236 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "P. Celinski and S.D. Cotofana and D. Abbott",
title = "Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic",
booktitle = "Proc. International Symposium on Circuits and Systems",
address = "Bangkok, Thailand",
month = "May",
year = "2003",
pages = "233-236"
}
author = "P. Celinski and S.D. Cotofana and D. Abbott",
title = "Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic",
booktitle = "Proc. International Symposium on Circuits and Systems",
address = "Bangkok, Thailand",
month = "May",
year = "2003",
pages = "233-236"
}