Computer Engineering Publications Database (2000-2018) Evaluation Methodology for Single Electron Encoded Threshold Logic Gates 
| Publication Type | Conference Paper |
|---|---|
| Title | Evaluation Methodology for Single Electron Encoded Threshold Logic Gates |
| Author(s) | C.R. Lageweg S.D. Cotofana S. Vassiliadis |
| Publication Date | December 2003 |
| Conference Name | International Conference on Very Large Scale Integration of System-on-Chip |
| Period | 1-3 December 2003 |
| Location | Darmstadt, Germany |
| ISBN | 3-901882-17-0 |
| Page Numbers | 258-262 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "C.R. Lageweg and S.D. Cotofana and S. Vassiliadis",
title = "Evaluation Methodology for Single Electron Encoded Threshold Logic Gates",
booktitle = "Proc. International Conference on Very Large Scale Integration of System-on-Chip",
address = "Darmstadt, Germany",
month = "December",
year = "2003",
pages = "258-262"
}
author = "C.R. Lageweg and S.D. Cotofana and S. Vassiliadis",
title = "Evaluation Methodology for Single Electron Encoded Threshold Logic Gates",
booktitle = "Proc. International Conference on Very Large Scale Integration of System-on-Chip",
address = "Darmstadt, Germany",
month = "December",
year = "2003",
pages = "258-262"
}