Computer Engineering Publications Database (2000-2018) Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates 
| Publication Type | Conference Paper |
|---|---|
| Title | Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates |
| Author(s) | P. Celinski S.D. Cotofana D. Abbott |
| Publication Date | November 2003 |
| Conference Name | 14th Annual Workshop on Circuits, Systems and Signal Processing |
| Period | 27-29 November 2003 |
| Location | Veldhoven, The Netherlands |
| ISBN | t.b.s. |
| Page Numbers | 43-48 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "P. Celinski and S.D. Cotofana and D. Abbott",
title = "Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates",
booktitle = "Proc. 14th Annual Workshop on Circuits, Systems and Signal Processing",
address = "Veldhoven, The Netherlands",
month = "November",
year = "2003",
pages = "43-48"
}
author = "P. Celinski and S.D. Cotofana and D. Abbott",
title = "Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates",
booktitle = "Proc. 14th Annual Workshop on Circuits, Systems and Signal Processing",
address = "Veldhoven, The Netherlands",
month = "November",
year = "2003",
pages = "43-48"
}