Design of a Pipelined and Parameterized VLIW Processor: ρ-VEX v.2 125_design_of_a_pipelined_and_parameterized_vliw_processor_rve.pdf

Publication TypeConference Paper
TitleDesign of a Pipelined and Parameterized VLIW Processor: ρ-VEX v.2
Author(s)R.A.E. Seedorf
F. Anjam
A.A.C. Brandon
S. Wong
Publication DateJanuary 2012
Conference Name6th HiPEAC Workshop on Reconfigurable Computing
Period24 January 2012
LocationParis, France
ISBNt.b.s.
Page Numbers12
publishedPublished
Selected PublicationNo
Note
Topic(s)None
Theme(s)Electronic System Level Design
Project(s)rVEX
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "R.A.E. Seedorf and F. Anjam and A.A.C. Brandon and S. Wong",
title = "Design of a Pipelined and Parameterized VLIW Processor: ρ-VEX v.2",
booktitle = "Proc. 6th HiPEAC Workshop on Reconfigurable Computing",
address = "Paris, France",
month = "January",
year = "2012",
pages = "12"
}