Computer Engineering Publications Database (2000-2018) Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy 
| Publication Type | Journal Paper |
|---|---|
| Title | Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy |
| Author(s) | S. Hamdioui A.J. van de Goor |
| Publication Date | October 2000 |
| Journal Name | Journal of Electronic Testing: Theory and Applications |
| Volume | 16 |
| Issue | 5 |
| Page Numbers | 487-498 |
| ISSN | 0923-8174 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@article{,
author = "S. Hamdioui and A.J. van de Goor",
title = "Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy",
journal = "Journal of Electronic Testing: Theory and Applications",
volume = "16",
issue = "5",
month = "October",
year = "2000",
pages = "487-498"
}
author = "S. Hamdioui and A.J. van de Goor",
title = "Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy",
journal = "Journal of Electronic Testing: Theory and Applications",
volume = "16",
issue = "5",
month = "October",
year = "2000",
pages = "487-498"
}