Computer Engineering Publications Database (2000-2018) A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs 
| Publication Type | Conference Paper |
|---|---|
| Title | A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs |
| Author(s) | L. Sterpone L. Carro D. Matos S. Wong F. Anjam |
| Publication Date | March 2011 |
| Conference Name | Design, Automation and Test in Europe |
| Period | 14-18 March 2011 |
| Location | Grenoble, France |
| ISBN | 978-3-9810801-7-9 |
| Page Numbers | |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | Adaptive Power/Performance Scaling |
| Theme(s) | Electronic System Level Design |
| Project(s) | ERA |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "L. Sterpone and L. Carro and D. Matos and S. Wong and F. Anjam",
title = "A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs",
booktitle = "Proc. Design, Automation and Test in Europe",
address = "Grenoble, France",
month = "March",
year = "2011",
pages = ""
}
author = "L. Sterpone and L. Carro and D. Matos and S. Wong and F. Anjam",
title = "A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs",
booktitle = "Proc. Design, Automation and Test in Europe",
address = "Grenoble, France",
month = "March",
year = "2011",
pages = ""
}