Computer Engineering Publications Database (2000-2018) System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs 
| Publication Type | Conference Paper |
|---|---|
| Title | System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs |
| Author(s) | K. Chandrasekar C. Weis B. Akesson N. Wehn K.G.W. Goossens |
| Publication Date | March 2013 |
| Conference Name | Design, Automation & Test in Europe Conference & Exhibition |
| Period | 18-22 March 2013 |
| Location | Grenoble, France |
| ISBN | t.b.a |
| Page Numbers | |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | 3D Stacking |
| Theme(s) | None |
| Project(s) | COMCAS |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "K. Chandrasekar and C. Weis and B. Akesson and N. Wehn and K.G.W. Goossens",
title = "System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs",
booktitle = "Proc. Design, Automation & Test in Europe Conference & Exhibition",
address = "Grenoble, France",
month = "March",
year = "2013",
pages = ""
}
author = "K. Chandrasekar and C. Weis and B. Akesson and N. Wehn and K.G.W. Goossens",
title = "System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs",
booktitle = "Proc. Design, Automation & Test in Europe Conference & Exhibition",
address = "Grenoble, France",
month = "March",
year = "2013",
pages = ""
}