Computer Engineering Publications Database (2000-2018) Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation
| Publication Type | Conference Paper |
|---|---|
| Title | Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation |
| Author(s) | A. Amaricai N. Cucu Laurenciu O. Boncalo J. Chen S. Nimara V. Savin S.D. Cotofana |
| Publication Date | November 2015 |
| Conference Name | XXX Conference on Design of Circuits and Integrated Systems |
| Period | 25-27 November 2015 |
| Location | Estoril, Portugal |
| ISBN | 978-1-4673-7229-9 |
| Page Numbers | |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | Dependable Nano Computing |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "A. Amaricai and N. Cucu Laurenciu and O. Boncalo and J. Chen and S. Nimara and V. Savin and S.D. Cotofana",
title = "Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation",
booktitle = "Proc. XXX Conference on Design of Circuits and Integrated Systems",
address = "Estoril, Portugal",
month = "November",
year = "2015",
pages = ""
}
author = "A. Amaricai and N. Cucu Laurenciu and O. Boncalo and J. Chen and S. Nimara and V. Savin and S.D. Cotofana",
title = "Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation",
booktitle = "Proc. XXX Conference on Design of Circuits and Integrated Systems",
address = "Estoril, Portugal",
month = "November",
year = "2015",
pages = ""
}