ρ-VEX on Chip: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File 1666_vex_on_chip_the_design_of_an_asic_for_a_dynamically_rec.pdf

Publication TypeMsc Thesis
Titleρ-VEX on Chip: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File
Author(s)L. van Bremen
Advisor(s)S. Wong
T.G.R.M. van Leuken
Z. Al-Ars
Publication DateAugust 2017
CE Thesis NumberCE-MS-2017-08
Selected PublicationNo
Note
Topic(s)None
Theme(s)None
Project(s)rVEX
Group(s)Computer Engineering

IEEE BibTex entry:
@mastersthesis{,
author = "L. van Bremen",
title = "ρ-VEX on Chip: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File",
school = "Delft University of Technology",
address = "Delft, Netherlands",
month = "August",
year = "2017"
}