Computer Engineering Publications Database (2000-2018) Test-architecture optimization for TSV-based 3D stacked ICs
| Publication Type | Conference Paper |
|---|---|
| Title | Test-architecture optimization for TSV-based 3D stacked ICs |
| Author(s) | B. Noia S.K. Goel K. Chakrabarty E.J. Marinissen J. Verbree |
| Publication Date | May 2010 |
| Conference Name | 15th IEEE European Test Symposium |
| Period | 25-28 May 2010 |
| Location | Prague, Czech Republic |
| ISBN | t.b.s. |
| Page Numbers | 24-29 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "B. Noia and S.K. Goel and K. Chakrabarty and E.J. Marinissen and J. Verbree",
title = "Test-architecture optimization for TSV-based 3D stacked ICs",
booktitle = "Proc. 15th IEEE European Test Symposium",
address = "Prague, Czech Republic",
month = "May",
year = "2010",
pages = "24-29"
}
author = "B. Noia and S.K. Goel and K. Chakrabarty and E.J. Marinissen and J. Verbree",
title = "Test-architecture optimization for TSV-based 3D stacked ICs",
booktitle = "Proc. 15th IEEE European Test Symposium",
address = "Prague, Czech Republic",
month = "May",
year = "2010",
pages = "24-29"
}