Computer Engineering Publications Database (2000-2018) Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers
| Publication Type | Conference Paper |
|---|---|
| Title | Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers |
| Author(s) | J. Verbree E.J. Marinissen P. Roussel D. Velenis |
| Publication Date | March 2010 |
| Conference Name | Design, Automation and Test in Europe |
| Period | 8-12 March 2010 |
| Location | Dresden, Germany |
| ISBN | n.a. |
| Page Numbers | 412-413 |
| published | Published |
| Selected Publication | No |
| Note | Poster at DATE 2010 Friday Workshop |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "J. Verbree and E.J. Marinissen and P. Roussel and D. Velenis",
title = "Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers",
booktitle = "Proc. Design, Automation and Test in Europe",
address = "Dresden, Germany",
month = "March",
year = "2010",
pages = "412-413"
}
author = "J. Verbree and E.J. Marinissen and P. Roussel and D. Velenis",
title = "Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers",
booktitle = "Proc. Design, Automation and Test in Europe",
address = "Dresden, Germany",
month = "March",
year = "2010",
pages = "412-413"
}