Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 350_assessing_fattree_topologies_for_regular_networkonchip_de.pdf

Publication TypeConference Paper
TitleAssessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints
Author(s)D. Ludovici
F. Gilabert
S. Medardoni
C.G. Requena
M.E. Gómez
P. López
D. Bertozzi
G.N. Gaydadjiev
Publication DateApril 2009
Conference NameDesign, Automation and Test in Europe
Period20-24 April 2009
LocationNice, France
ISBNt.b.s.
Page Numbers562-565
publishedPublished
Selected PublicationNo
Note
Topic(s)None
Theme(s)None
Project(s)None
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "D. Ludovici and F. Gilabert and S. Medardoni and C.G. Requena and M.E. Gómez and P. López and D. Bertozzi and G.N. Gaydadjiev",
title = "Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints",
booktitle = "Proc. Design, Automation and Test in Europe",
address = "Nice, France",
month = "April",
year = "2009",
pages = "562-565"
}