3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip 369_3tier_reconfiguration_model_for_fpgas_using_hardwired_netwo.pdf

Publication TypeConference Paper
Title3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip
Author(s)M.A. Wahlah
K.G.W. Goossens
Publication DateDecember 2009
Conference NameInternational Conference on Field-Programmable Technology
Period9-11 December 2009
LocationSidney, Australia
ISBNt.b.s.
Page Numbers
publishedPublished
Selected PublicationNo
Note
Topic(s)None
Theme(s)None
Project(s)None
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "M.A. Wahlah and K.G.W. Goossens",
title = "3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip",
booktitle = "Proc. International Conference on Field-Programmable Technology",
address = "Sidney, Australia",
month = "December",
year = "2009",
pages = ""
}