A Performance Model for Network Processor Architectures in Packet Processing Systems 660_a_performance_model_for_network_processor_architectures_in_p.pdf

Publication TypeConference Paper
TitleA Performance Model for Network Processor Architectures in Packet Processing Systems
Author(s)M. Ahmadi
S. Wong
Publication DateNovember 2007
Conference Name19th IASTED International Conference on Parallel and Distributed Computing and Systems
Period19–21 November 2007
LocationCambridge, USA
ISBNt.b.s.
Page Numbers176-181
publishedPublished
Selected PublicationNo
Note
Topic(s)None
Theme(s)None
Project(s)None
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "M. Ahmadi and S. Wong",
title = "A Performance Model for Network Processor Architectures in Packet Processing Systems",
booktitle = "Proc. 19th IASTED International Conference on Parallel and Distributed Computing and Systems",
address = "Cambridge, USA",
month = "November",
year = "2007",
pages = "176-181"
}