Computer Engineering Publications Database (2000-2018) A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme 
| Publication Type | Conference Paper |
|---|---|
| Title | A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme |
| Author(s) | M. Berekovic T. Niggemeier |
| Publication Date | July 2006 |
| Conference Name | 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation |
| Period | 17-20 July 2006 |
| Location | Samos, Greece |
| ISBN | 3-540-36410-2 |
| Page Numbers | |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "M. Berekovic and T. Niggemeier",
title = "A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme",
booktitle = "Proc. 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation",
address = "Samos, Greece",
month = "July",
year = "2006",
pages = ""
}
author = "M. Berekovic and T. Niggemeier",
title = "A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme",
booktitle = "Proc. 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation",
address = "Samos, Greece",
month = "July",
year = "2006",
pages = ""
}