Computer Engineering Publications Database (2000-2018) Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic 
| Publication Type | Conference Paper |
|---|---|
| Title | Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic |
| Author(s) | P. Celinski D. Abbott S.D. Cotofana |
| Publication Date | September 2004 |
| Conference Name | 14th International Workshop on Power and Timing Modeling, Optimization and Simulation |
| Period | 15-17 September 2004 |
| Location | Santorini, Greece |
| ISBN | 3-540-23095-5 |
| Page Numbers | 899-906 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "P. Celinski and D. Abbott and S.D. Cotofana",
title = "Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic",
booktitle = "Proc. 14th International Workshop on Power and Timing Modeling, Optimization and Simulation",
address = "Santorini, Greece",
month = "September",
year = "2004",
pages = "899-906"
}
author = "P. Celinski and D. Abbott and S.D. Cotofana",
title = "Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic",
booktitle = "Proc. 14th International Workshop on Power and Timing Modeling, Optimization and Simulation",
address = "Santorini, Greece",
month = "September",
year = "2004",
pages = "899-906"
}