Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation 1044_optimizing_stresses_for_testing_dram_cell_defects_using_ele.pdf

Publication TypeConference Paper
TitleOptimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
Author(s)Z. Al-Ars
A.J. van de Goor
J. Braun
D. Richter
Publication DateMarch 2003
Conference NameDesign, Automation and Test in Europe Conference and Exposition
Period3-7 March 2003
LocationMunich, Germany
ISBN0-7695-1870-2
Page Numbers484-489
publishedPublished
Selected PublicationNo
Note
Topic(s)None
Theme(s)None
Project(s)None
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "Z. Al-Ars and A.J. van de Goor and J. Braun and D. Richter",
title = "Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation",
booktitle = "Proc. Design, Automation and Test in Europe Conference and Exposition",
address = "Munich, Germany",
month = "March",
year = "2003",
pages = "484-489"
}