Computer Engineering Publications Database (2000-2018) Compact Delay Modeling of Latch-based Threshold Logic Gates 
| Publication Type | Conference Paper |
|---|---|
| Title | Compact Delay Modeling of Latch-based Threshold Logic Gates |
| Author(s) | M.D. Padure S.D. Cotofana C. Dan S. Vassiliadis M. Bodea |
| Publication Date | October 2002 |
| Conference Name | International Semiconductor Conference |
| Period | 8-12 October 2002 |
| Location | Sinaia, Romania |
| ISBN | 0-7803-7440-1 |
| Page Numbers | 317-320 |
| published | Published |
| Selected Publication | No |
| Note | Best Paper Award |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "M.D. Padure and S.D. Cotofana and C. Dan and S. Vassiliadis and M. Bodea",
title = "Compact Delay Modeling of Latch-based Threshold Logic Gates",
booktitle = "Proc. International Semiconductor Conference",
address = "Sinaia, Romania",
month = "October",
year = "2002",
pages = "317-320"
}
author = "M.D. Padure and S.D. Cotofana and C. Dan and S. Vassiliadis and M. Bodea",
title = "Compact Delay Modeling of Latch-based Threshold Logic Gates",
booktitle = "Proc. International Semiconductor Conference",
address = "Sinaia, Romania",
month = "October",
year = "2002",
pages = "317-320"
}