TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems 1332_tlm_modelling_of_3d_stacked_wide_io_dram_subsystems.pdf

Publication TypeConference Paper
TitleTLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
Author(s)M. Jung
C. Weis
K. Chandrasekar
N. Wehn
Publication DateJanuary 2013
Conference Name5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Period21 January 2013
LocationBerlin, Germany
ISBNt.b.a
Page Numbers
publishedPublished
Selected PublicationNo
Note
Topic(s)Architecture Virtualization
3D Stacking
Theme(s)None
Project(s)None
Group(s)Computer Engineering

IEEE BibTex entry:
@inproceedings{,
author = "M. Jung and C. Weis and K. Chandrasekar and N. Wehn",
title = "TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems",
booktitle = "Proc. 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools",
address = "Berlin, Germany",
month = "January",
year = "2013",
pages = ""
}