TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
Publication Type | Conference Paper |
---|---|
Title | TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems |
Author(s) | M. Jung C. Weis K. Chandrasekar N. Wehn |
Publication Date | January 2013 |
Conference Name | 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools |
Period | 21 January 2013 |
Location | Berlin, Germany |
ISBN | t.b.a |
Page Numbers | |
published | Published |
Selected Publication | No |
Note | |
Topic(s) | Architecture Virtualization 3D Stacking |
Theme(s) | None |
Project(s) | None |
Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "M. Jung and C. Weis and K. Chandrasekar and N. Wehn",
title = "TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems",
booktitle = "Proc. 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools",
address = "Berlin, Germany",
month = "January",
year = "2013",
pages = ""
}
author = "M. Jung and C. Weis and K. Chandrasekar and N. Wehn",
title = "TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems",
booktitle = "Proc. 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools",
address = "Berlin, Germany",
month = "January",
year = "2013",
pages = ""
}