Computer Engineering Publications Database (2000-2018) An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1} 
| Publication Type | Journal Paper |
|---|---|
| Title | An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1} |
| Author(s) | K.A. Gbolagade G.R. Voicu S.D. Cotofana |
| Publication Date | August 2011 |
| Journal Name | IEEE Transactions On Very Large Scale Integration (VLSI) Systems |
| Volume | 19 |
| Issue | 8 |
| Page Numbers | 1500-1503 |
| ISSN | 1063-8210 |
| published | Published |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@article{,
author = "K.A. Gbolagade and G.R. Voicu and S.D. Cotofana",
title = "An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1}",
journal = "IEEE Transactions On Very Large Scale Integration (VLSI) Systems",
volume = "19",
issue = "8",
month = "August",
year = "2011",
pages = "1500-1503"
}
author = "K.A. Gbolagade and G.R. Voicu and S.D. Cotofana",
title = "An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1}",
journal = "IEEE Transactions On Very Large Scale Integration (VLSI) Systems",
volume = "19",
issue = "8",
month = "August",
year = "2011",
pages = "1500-1503"
}