Computer Engineering Publications Database (2000-2018) A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support 
| Publication Type | Msc Thesis |
|---|---|
| Title | A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support |
| Author(s) | J. van Straten |
| Advisor(s) | S. Wong K.L.M. Bertels T.G.R.M. van Leuken S. Hamdioui |
| Publication Date | May 2016 |
| CE Thesis Number | CE-MS-2016-06 |
| Selected Publication | No |
| Note | |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | rVEX |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@mastersthesis{,
author = "J. van Straten",
title = "A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support",
school = "Delft University of Technology",
address = "Delft, Netherlands",
month = "May",
year = "2016"
}
author = "J. van Straten",
title = "A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support",
school = "Delft University of Technology",
address = "Delft, Netherlands",
month = "May",
year = "2016"
}