Computer Engineering Publications Database (2000-2018) Buffer Design Trade-Offs for Single Electron Logic Gates 
| Publication Type | Conference Paper |
|---|---|
| Title | Buffer Design Trade-Offs for Single Electron Logic Gates |
| Author(s) | C.R. Lageweg S.D. Cotofana S. Vassiliadis |
| Publication Date | July 2005 |
| Conference Name | 5th IEEE Conference on Nanotechnology |
| Period | 11-15 July 2005 |
| Location | Nagoya, Japan |
| ISBN | 0-7803-9199-3 |
| Page Numbers | |
| published | Published |
| Selected Publication | No |
| Note | Best Paper Award |
| Topic(s) | None |
| Theme(s) | None |
| Project(s) | None |
| Group(s) | Computer Engineering |
IEEE BibTex entry:
@inproceedings{,
author = "C.R. Lageweg and S.D. Cotofana and S. Vassiliadis",
title = "Buffer Design Trade-Offs for Single Electron Logic Gates",
booktitle = "Proc. 5th IEEE Conference on Nanotechnology",
address = "Nagoya, Japan",
month = "July",
year = "2005",
pages = ""
}
author = "C.R. Lageweg and S.D. Cotofana and S. Vassiliadis",
title = "Buffer Design Trade-Offs for Single Electron Logic Gates",
booktitle = "Proc. 5th IEEE Conference on Nanotechnology",
address = "Nagoya, Japan",
month = "July",
year = "2005",
pages = ""
}