D Sabena, L. Sterpone, M Schölzel, T Koal, H T Vierhaus, S. Wong, R Glein, F Rittner, C Stender, M. Porrmann, J Hagemeyer, Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications? (May 2014), 19th IEEE European Test Symposium (ETS 2014), 26-30 May 2014 , Paderborn, Germany [Conference Paper]

L. Sterpone, L. Carro, D. Matos, S. Wong, F. Anjam, A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs (March 2011), Design, Automation and Test in Europe (DATE 2011), 14-18 March 2011, Grenoble, France [Conference Paper]