A.G.M. Cilio
Name | A.G.M. Cilio |
---|---|
First Name | Andrea |
Author Type | Phd Student |
Affiliation | TU Delft |
Publications
A.G.M. Cilio, H. Corporaal,
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
(April 2002),
11th International Conference on Compiler Construction (CC 2002), 8-12 April 2002, Grenoble, France
[Conference Paper]
I. Antochi, B.H.H. Juurlink, A.G.M. Cilio, P. Liuha,
Trading efficiency for energy in a texture cache architecture
(April 2002),
4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy
[Conference Paper]
I. Antochi, B.H.H. Juurlink, A.G.M. Cilio,
A low-cost, power-efficient texture cache architecture
(November 2001),
12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
A.G.M. Cilio, H. Corporaal,
Code Positioning for VLIW Architectures
(June 2001),
9th International Conference and Exibition on High-Performance Computing and Networking (HPCN Europe 2001), 25-27 June 2001, Amsterdam, The Netherlands
[Conference Paper]
A.G.M. Cilio, H. Corporaal,
The Impact of Code Positioning on ILP Scheduling
(June 2000),
6th Annual conference of the Advanced School for Computing and Imaging (ASCI 2000), 14-16 June 2000, Lommel, Belgium
[Conference Paper]
A.G.M. Cilio, H. Corporaal,
Link-time effective whole-program optimizations
(March 2000),
Future Generation Computer Systems (FGCS), volume 16, issue 5
[Journal Paper]