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I. Antochi

NameI. Antochi
First NameIosif
E-mail
Author TypePhd Student
AffiliationTU Delft

Publications

B.H.H. Juurlink, I. Antochi, D. Crisu, S.D. Cotofana, GRAAL: A Framework for Low-Power 3D Graphics Accelerators (July 2008), IEEE Computer Graphics and Applications (CGA), volume 28, issue 4 [Journal Paper]
I. Antochi, Suitability of Tile-Based Rendering for Low-Power 3D Graphics Accelerators 693_suitability_of_tilebased_rendering_for_lowpower_3d_graphic.pdf (October 2007), [Phd Thesis]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient State Management for Tile-Based 3D Graphics Architectures 974_efficient_state_management_for_tilebased_3d_graphics_archit.pdf (November 2004), 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient Tile-Aware Bounding-Box Overlap Test for Tile Based Rendering 975_efficient_tileaware_boundingbox_overlap_test_for_tile_base.pdf (November 2004), International Symposium on System-on-Chip (SOC 2004), 16-18 November 2004, Tampere, Finland [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Scene Management Models and Overlap Tests for Tile-Based Rendering 908_scene_management_models_and_overlap_tests_for_tilebased_ren.pdf (August 2004), 7th Euromicro Symposium on Digital Systems Design (DSD 2004), 31 August - 3 September 2004, Rennes, France [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Memory Bandwidth Requirements of Tile-Based Rendering 921_memory_bandwidth_requirements_of_tilebased_rendering.pdf (July 2004), 4th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2004), 19-21 July 2004, Samos, Greece [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, GraalBench: A 3D Graphics Benchmark Suite for Mobile Phones 929_graalbench_a_3d_graphics_benchmark_suite_for_mobile_phones.pdf (June 2004), ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), 11-13 June 2004, Washington DC, USA [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, 3D Graphics Benchmarks for Low-Power Architectures 1060_3d_graphics_benchmarks_for_lowpower_architectures.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, A Flexible Simulator for Exploring Hardware Rasterizers 1149_a_flexible_simulator_for_exploring_hardware_rasterizers.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, Selecting the optimal tile size for low-power tile-based rendering 1145_selecting_the_optimal_tile_size_for_lowpower_tilebased_re.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
I. Antochi, B.H.H. Juurlink, A.G.M. Cilio, P. Liuha, Trading efficiency for energy in a texture cache architecture 1120_trading_efficiency_for_energy_in_a_texture_cache_architectu.pdf (April 2002), 4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy [Conference Paper]
I. Antochi, B.H.H. Juurlink, S. Vassiliadis, A low power 2D/3D graphics accelerator; A preliminary ISA (January 2002), CE technical report [Technical Report]
I. Antochi, B.H.H. Juurlink, A.G.M. Cilio, A low-cost, power-efficient texture cache architecture 1226_a_lowcost_powerefficient_texture_cache_architecture.pdf (November 2001), 12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands [Conference Paper]