J. Yu, R. Nane, I. Ashraf, M. Taouil, S. Hamdioui, H. Corporaal, K.L.M. Bertels, Skeleton-based Synthesis Flow for Computation-In-Memory Architectures (October 2017), IEEE Transactions on Emerging Topics in Computing, volume PP, issue 99 , Pre-publish [Journal Paper]

S. Hamdioui, S. Kvatinsky, G Cauwenberghs, L. Xie, N. Wald , S. Joshi, H. M. Elsayed, H. Corporaal, K.L.M. Bertels, Memristor for computing: Myth or reality? (March 2017), Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland [Conference Proceedings]

S. Hamdioui, S Kvatinsky, G Cauwenberghs, L. Xie, N Wald, S Joshi, H Elsayed, H. Corporaal, K.L.M. Bertels, Memristor For Computing: Myth or Reality? (March 2017), Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland [Conference Proceedings]

J. Yu, R. Nane, M.A.B. Haron, S. Hamdioui, H. Corporaal, K.L.M. Bertels, Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China , Best Student Paper Award [Conference Proceedings]

A.T. Nelson, A. Hansson, H. Corporaal, K.G.W. Goossens, Conservative Application-Level Performance Analysis through Simulation of MPSoCs (October 2010), 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2010), 28-29 October 2010, Scottsdale, USA [Conference Paper]

S. Roos, H. Corporaal, R. Lamberts, Clustering on the Move (April 2002), 4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy [Conference Paper]

A.G.M. Cilio, H. Corporaal, Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation (April 2002), 11th International Conference on Compiler Construction (CC 2002), 8-12 April 2002, Grenoble, France [Conference Paper]

A.G.M. Cilio, H. Corporaal, Code Positioning for VLIW Architectures (June 2001), 9th International Conference and Exibition on High-Performance Computing and Networking (HPCN Europe 2001), 25-27 June 2001, Amsterdam, The Netherlands [Conference Paper]

T.D. Hamalainen, M. Hannikainen, P. Hamalainen, H. Corporaal, J. Saarinen, Implementation of encryption algorithms on transport triggered architectures (May 2001), International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sidney, Australia [Conference Paper]

M. Arnold, H. Corporaal, Designing domain-specific processors (April 2001), 9th International Sympsium on Hardware/Software Codesign (CODES 2001), 25-27 April 2001, Copenhagen, Denmark [Conference Paper]

M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Hashed Addressed Caches for Embedded Pointer Based Codes (August 2000), 6th International Euro-Par Conference on Parallel Processing (Euro-Par 2000), 29 August - 1 September 2000, Munich, Germany [Conference Paper]

H.J.M. Schot, H. Corporaal, Automated design of an ASIP for image processing applications (August 2000), 6th International Euro-Par Conference on Parallel Processing (Euro-Par 2000), 29 August - 1 September 2000, Munich, Germany [Conference Paper]

R. Manniesing, I. Karkowski, H. Corporaal, Automatic SIMD parallelization of embedded applications based on pattern recognition (August 2000), 6th International Euro-Par Conference on Parallel Processing (Euro-Par 2000), 29 August - 1 September 2000, Munich, Germany [Conference Paper]

A.G.M. Cilio, H. Corporaal, The Impact of Code Positioning on ILP Scheduling (June 2000), 6th Annual conference of the Advanced School for Computing and Imaging (ASCI 2000), 14-16 June 2000, Lommel, Belgium [Conference Paper]

H. Corporaal, Embedded processor design using transport triggered architectures (June 2000), International Workshop on Spectral Transforms and Logic Design for Future Digital Systems (SPECLOG 2000), 2-3 June 2000, Tampere, Finland [Conference Paper]

A.G.M. Cilio, H. Corporaal, Link-time effective whole-program optimizations (March 2000), Future Generation Computer Systems (FGCS), volume 16, issue 5 [Journal Paper]

M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]