A. Strano, C.G. Requena, D. Ludovici, M.E. Gómez, M. Favalli, D. Bertozzi, Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture (March 2011), Design, Automation and Test in Europe (DATE 2011), 14-18 March 2011, Grenoble, France [Conference Paper]

D. Ludovici, F. Gilabert, M.E. Gómez, G.N. Gaydadjiev, D. Bertozzi, Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology (December 2010), 3rd ACM/IEEE International Workshop on Network-on-Chip Architectures (NoCArc 2010), 4 December 2010, Atlanta, USA [Conference Paper]

F. Gilabert, D. Ludovici, M.E. Gómez, D. Bertozzi, Topology Exploration (December 2010), Book Title "Designing Network-on-Chip Architectures in the Nanoscale Era", Published by CRC Press [Book Chapter]

D. Ludovici, F. Gilabert, S. Medardoni, C.G. Requena, M.E. Gómez, P. López, D. Bertozzi, G.N. Gaydadjiev, Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints (April 2009), Design, Automation and Test in Europe (DATE 2009), 20-24 April 2009, Nice, France [Conference Paper]

D. Ludovici, F. Gilabert, C.G. Requena, M.E. Gómez, P. López, G.N. Gaydadjiev, J. Duato, Butterfly vs. Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs (January 2009), 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2009), 25-28 January 2009, Paphos, Cyprus [Conference Paper]