D. Ludovici, Technology Aware Network-on-Chip Connectivity and Synchronization Design (June 2011), [Phd Thesis]

A. Strano, C.G. Requena, D. Ludovici, M.E. Gómez, M. Favalli, D. Bertozzi, Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture (March 2011), Design, Automation and Test in Europe (DATE 2011), 14-18 March 2011, Grenoble, France [Conference Paper]

D. Ludovici, A. Strano, G.N. Gaydadjiev, D. Bertozzi, Mesochronous NoC Technology for Power-Efficient GALS MPSoCs (January 2011), 5th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece [Conference Paper]

D. Ludovici, F. Gilabert, M.E. Gómez, G.N. Gaydadjiev, D. Bertozzi, Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology (December 2010), 3rd ACM/IEEE International Workshop on Network-on-Chip Architectures (NoCArc 2010), 4 December 2010, Atlanta, USA [Conference Paper]

D. Bertozzi, A. Strano, D. Ludovici, V. Pavlidis, F. Angiolini, M. Krstic, The Synchronization Challenge (December 2010), Book Title "Designing Network-on-Chip Architectures in the Nanoscale Era", Published by CRC Press [Book Chapter]

F. Gilabert, D. Ludovici, M.E. Gómez, D. Bertozzi, Topology Exploration (December 2010), Book Title "Designing Network-on-Chip Architectures in the Nanoscale Era", Published by CRC Press [Book Chapter]

A. Strano, D. Ludovici, D. Bertozzi, A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design (July 2010), International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS X), 19-22 July 2010, Samos, Greece [Conference Paper]

D. Ludovici, A. Strano, G.N. Gaydadjiev, L. Benini, D. Bertozzi, Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs, (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany [Conference Paper]

D. Ludovici, A. Strano, D. Bertozzi, Architecture Design Principles for the Integration of Synchronization Interfaces into Network-on-Chip Switches (December 2009), 2nd ACM/IEEE International Workshop on Network-on-Chip Architectures (NoCArc 2009), 12 December 2009, New York, USA [Conference Paper]

D. Ludovici, D. Bertozzi, L. Benini, Capturing Topology-Level Implications of Link Synthesis Techniques for Nanoscale Networks-on-Chip (May 2009), 19th ACM Great Lakes Symposium on VLSI (GLSVLSI 2009), 10-12 May 2009, Boston, USA [Conference Paper]

D. Ludovici, A. Strano, D. Bertozzi, L. Benini, G.N. Gaydadjiev, Comparing Tightly and Loosely Coupled Mesochronous Synchronizers in a NoC Switch Architecture (May 2009), 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2009), 10-13 May 2009, San Diego, USA [Conference Paper]

D. Ludovici, F. Gilabert, S. Medardoni, C.G. Requena, M.E. Gómez, P. López, D. Bertozzi, G.N. Gaydadjiev, Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints (April 2009), Design, Automation and Test in Europe (DATE 2009), 20-24 April 2009, Nice, France [Conference Paper]

F. Gilabert, D. Ludovici, S. Medardoni, D. Bertozzi, L. Benini, G.N. Gaydadjiev, Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints (March 2009), International Workshop on Multi-Core Computing Systems (MuCoCoS 20009), 16 March 2009, Fukuoka, Japan [Conference Paper]

D. Ludovici, F. Gilabert, C.G. Requena, M.E. Gómez, P. López, G.N. Gaydadjiev, J. Duato, Butterfly vs. Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs (January 2009), 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2009), 25-28 January 2009, Paphos, Cyprus [Conference Paper]

D. Ludovici, G. Keramidas, G.N. Gaydadjiev, S. Kaxiras, Integration of Power Saving Techniques in the UNISIM Simulation Framework through the Shadow Module design paradigm (January 2009), 1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2009), January 2009, Paphos, Cyprus [Conference Paper]

D. Ludovici, G.N. Gaydadjiev, SARC Power Estimation Methodology (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]

D. Ludovici, Performance Analysis of RR and FQ Algorithms in Reconfigurable Routers (December 2006), [Msc Thesis]

D. Ludovici, S. Wong, Performance Analysis of RR and FQ Algorithms in Reconfigurable Routers (November 2006), 17th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006), 23-24 November 2006, Veldhoven, The Netherlands [Conference Paper]