M. Berekovic

NameM. Berekovic
First NameMladen
E-mail
Author TypeExternal
AffiliationTU Braunschweig

Publications

F. Pratas, G.N. Gaydadjiev, M. Berekovic, L.A. Sousa, S. Kaxiras, Low Power Microarchitecture with Instruction Reuse 477_low_power_microarchitecture_with_instruction_reuse.pdf (May 2008), 5th Conference on Computing Frontiers (CF 2008), 5-7 May 2008, Ischia, Italy [Conference Paper]
F.J. Bouwens, M. Berekovic, B. de Sutter, G.N. Gaydadjiev, Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array 552_architecture_enhancements_for_the_adres_coarsegrained_recon.pdf (January 2008), 3rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2008), 27-29 January 2008, Göteborg, Sweden [Conference Paper]
S. Vassiliadis, M. Berekovic, T.D. Hamalainen, Proceedings of SAMOS 2007 workshop (July 2007), 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2007), 16-19 July 2007, Samos, Greece [Conference Proceedings]
L. Ysebodt, M. de Nil, J. Huisken, M. Berekovic, Q. Zhao, F.J. Bouwens, J. van Meerbergen, Design of Low Power Wireless Sensor Nodes on Energy Scanvengers for Biomedical Monitoring 612_design_of_low_power_wireless_sensor_nodes_on_energy_scanveng.pdf (July 2007), 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2007), 16-19 July 2007, Samos, Greece [Conference Paper]
C. Arbelo, A. Kanstein, S. Lopez, J.F. Lopez, M. Berekovic, R. Sarmiento, J.Y. Mignolet, Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264 Deblocking Filter 626_mapping_controlintensive_video_kernels_onto_a_coarsegrain.pdf (April 2007), Design, Automation and Test in Europe Conference and Exposition (DATE 2007), 16-20 April 2007, Nice, France [Conference Paper]
K. Wu, A. Kanstein, J. Madsen, M. Berekovic, MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture 636_mtadres_multithreading_on_coarsegrained_reconfigurable_ar.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
F.J. Bouwens, M. Berekovic, A. Kanstein, G.N. Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
H. Hermandez, A. Kanstein, S. Lopez, J.F. Lopez, M. Berekovic, R. Sarmiento, J.Y. Mignolet, Mapping of the H.264/AVC Motion Compensation Algorithm onto a Coarse-Grain Reconfigurable Array (November 2006), 21st Conference on Design of Circuits and Integrated Systems (DCIS 2006), 22-24 November 2006, Barcelona, Spain [Conference Paper]
M. Berekovic, T. Niggemeier, A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme 716_a_scalable_multithread_multiissue_array_processor_archit.pdf (July 2006), 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), 17-20 July 2006, Samos, Greece [Conference Paper]