B. Yang, S. Grandhi, C. Spagnol, E. Popovici, S.D. Cotofana, An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability (June 2016), 27th Irish Signals and Systems Conference (ISSC), 21-22 June 2016, Derry, Ireland [Conference Paper]

J. Chen, S.D. Cotofana, S. Grandhi, C. Spagnol, E. Popovici, Inverse Gaussian Distribution Based Timing Analysis of Sub-Threshold CMOS Circuits (December 2015), Microelectronics Reliability, volume 55, issue 12 [Journal Paper]

S. Grandhi, D. McCarthy, C. Spagnol, E. Popovici, S.D. Cotofana, ROST-C: Reliability Driven Optimisation and Synthesis Techniques for Combinational Circuits (October 2015), 33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA [Conference Paper]

T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana, Transmission Channel Noise Aware Energy Effective LDPC Decoding (October 2015), Book Title "VLSI-SoC: Internet of Things Foundations", Published by Springer International Publishing [Book Chapter]

T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana, Towards Energy Effective LDPC Decoding by Exploiting Channel Noise Variability (October 2014), 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2014), 6-8 October 2014, Playa del Carmen, Mexico [Conference Paper]

S. Grandhi, C. Spagnol, J. Chen, E. Popovici, S.D. Cotofana, Reliability Aware Logic Synthesis through Rewriting (September 2014), 27th International IEEE SoC (System-on-Chip) Conference (SOCC), 2-5 September, Las Vegas, USA [Conference Paper]

J. Chen, C. Spagnol, S. Grandhi, E. Popovici, A. Amaricai, S.D. Cotofana, Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits (July 2014), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), 9-11 July 2014, Tampa, USA [Conference Paper]