S.D. Cotofana
Name | S.D. Cotofana |
---|---|
First Name | Sorin |
S.D.Cotofana@tudelft.nl | |
Author Type | Staff |
Affiliation | TU Delft |
Publications
Y. Jiang, N. Cucu Laurenciu, S.D. Cotofana,
On Basic Boolean Function Graphene Nanoribbon Conductance Mapping
(December 2018),
IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCAS I)
[Journal Paper]
N. Cucu Laurenciu, S.D. Cotofana,
On Effective Graphene based Computing
(October 2018),
41st International Semiconductor Conference (CAS 2018), 10-12 October 2018, Sinaia, Romania
[Conference Paper]
Y. Jiang, N. Cucu Laurenciu, S.D. Cotofana,
Complementary Arranged Graphene Nanoribbon-based Boolean Gates
(July 2018),
14th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018), 17-19 July 2018, Athens, Greece
[Conference Paper]
Y. Jiang, N. Cucu Laurenciu, S.D. Cotofana,
Non-Equilibrium Green Function-based Verilog-A Graphene Nanoribbon Model
(July 2018),
18th IEEE International Conference on Nanotechnology (IEEE NANO 2018), 23-26 July 2018, Cork, Ireland
[Conference Paper]
Y. Jiang, N. Cucu Laurenciu, S.D. Cotofana,
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps
(May 2018),
IEEE International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence
[Conference Paper]
M. Lefter, G.R. Voicu, T. Marconi, V. Savin, S.D. Cotofana,
LDPC-Based Adaptive Multi-Error Correction for 3D Memories
(September 2017),
35th IEEE International Conference on Computer Design (ICCD 2017), 5-8 November 2017, Boston, USA
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Haar-based Interconnect Coding for Energy Effective Medium/Long Range Data Transport
(September 2017),
30th IEEE International System-on-Chip Conference (SOCC 2017), 5-8 September 2017, Munich, Germany
[Conference Paper]
M. Lefter, T. Marconi, G.R. Voicu, S.D. Cotofana,
Low Cost Multi-Error Correction for 3D Polyhedral Memories
(July 2017),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2017), 25-26 July 2017, Newporrt, USA
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Fast and Accurate Workload-Level Neural Network Based IC Energy Consumption Estimation
(June 2017),
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2017), 12-15 June 2017, Taormina, Italy
[Conference Paper]
A. Makosiej, N. Gupta, N. Vakul, A. Vladimirescu, S.D. Cotofana, S. Mahapatra, A. Amara, C. Anghel,
Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications
(December 2016),
Micro & Nano Letters, volume 11
, doi:10.1049/mnl.2016.0442
[Journal Paper]
J. Lee, F. Peper, S.D. Cotofana, M. Naruse, M. Ohtsu, T. Kawazoe, Y. Takahashi, T. Shimokawa, L. B. Kish, T. Kubota,
Brownian Circuits: Designs
(December 2016),
International Journal of Unconventional Computing (IJUC), volume 12, issue 5-6
[Journal Paper]
T. T. Nguyen-Ly, T. Gupta, M. Pezzin, V. Savin, D. Declercq, S.D. Cotofana,
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units
(September 2016),
19th Euromicro Conference on Digital Systems Design (DSD 2016), 31 August - 2 September, Limassol, Cyprus
, 10.1109/DSD.2016.33
[Conference Paper]
C. Chen, Y. Fu, S.D. Cotofana,
”Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links”
(August 2016),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
, DOI: 10.1109/TCAD.2016.2570680
[Journal Paper]
G.R. Voicu, S.D. Cotofana,
High-performance, Cost-effective 3D Stacked Wide-Operand Adders
(August 2016),
IEEE Transactions on Emerging Topics in Computing
, DOI: 10.1109/TETC.2016.2598290
[Journal Paper]
N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, S.D. Cotofana, C. Anghel,
TFET NDR Skewed Inverter based Sensing Method
(July 2016),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China
, Best Concept Paper Award
[Conference Paper]
B. Yang, M. A. Quille, A. Amann, E. Popovici, S.D. Cotofana,
A supply voltage-dependent variation aware reliability evaluation model
(July 2016),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China
[Conference Paper]
M. Enachescu, M. Lefter, G.R. Voicu, S.D. Cotofana,
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory
(July 2016),
IEEE Transactions on Emerging Topics in Computing
, DOI: 10.1109/TETC.2016.2588725
[Journal Paper]
N. Cucu Laurenciu, T. Gupta, V. Savin, S.D. Cotofana,
Error Correction Code Protected Data Processing Units
(July 2016),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China
[Conference Paper]
B. Yang, S. Grandhi, C. Spagnol, E. Popovici, S.D. Cotofana,
An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability
(June 2016),
27th Irish Signals and Systems Conference (ISSC), 21-22 June 2016, Derry, Ireland
[Conference Paper]
J. Chen, S.D. Cotofana, S. Grandhi, C. Spagnol, E. Popovici,
Inverse Gaussian Distribution Based Timing Analysis of Sub-Threshold CMOS Circuits
(December 2015),
Microelectronics Reliability, volume 55, issue 12
[Journal Paper]
A. Amaricai, N. Cucu Laurenciu, O. Boncalo, J. Chen, S. Nimara, V. Savin, S.D. Cotofana,
Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation
(November 2015),
XXX Conference on Design of Circuits and Integrated Systems (DCIS 2015), 25-27 November 2015, Estoril, Portugal
[Conference Paper]
A. Amaricai, V. Savin, O. Boncalo, N. Cucu Laurenciu, J. Chen, S.D. Cotofana,
Timing Error Analysis of Flooded LDPC Decoders
(November 2015),
IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS), 2-4 November 2015, Tel-Aviv, Israel
[Conference Paper]
S. Grandhi, D. McCarthy, C. Spagnol, E. Popovici, S.D. Cotofana,
ROST-C: Reliability Driven Optimisation and Synthesis Techniques for Combinational Circuits
(October 2015),
33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA
[Conference Paper]
T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana,
Transmission Channel Noise Aware Energy Effective LDPC Decoding
(October 2015),
Book Title "VLSI-SoC: Internet of Things Foundations", Published by Springer International Publishing
[Book Chapter]
T. Marconi, S.D. Cotofana,
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding
(May 2015),
ACM Great Lakes VLSI Symposium (GLSVLSI 2015), 20-22 May 2015, Pittsburgh, USA
[Conference Paper]
M. Lefter, G.R. Voicu, S.D. Cotofana,
A Shared Polyhedral Cache for 3D Wide-I/O Multi-Core Computing Platforms
(May 2015),
IEEE International Symposium on Circuits and Systems (ISCAS 2015), 24-27 May 2015, Lisbon, Portugal
[Conference Paper]
J. Chen, A. Tisserand, E. Popovici, S.D. Cotofana,
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier
(May 2015),
21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 4-6 May 2015, Mountain View, Silicon Valley, California, USA
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Low Cost and Energy, Thermal Noise Driven, Probability Modulated Random Number Generator
(May 2015),
IEEE International Symposium on Circuits and Systems (ISCAS 2015), 24-27 May 2015, Lisbon, Portugal
[Conference Paper]
C. Chen, M. Enachescu, S.D. Cotofana,
Enabling Vertical Wormhole Switching in 3D NoC-Bus Hybrid Systems
(March 2015),
18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France
[Conference Paper]
A. Gheolbanoiu, L Petrica, S.D. Cotofana,
Hybrid Adaptive Clock Management for FPGA Processor Acceleration
(March 2015),
18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France
[Conference Paper]
H. Siewobr, K.A. Gbolagade, S.D. Cotofana,
An efficient residue-to-binary converter for the new moduli set {2^{n/2} ± 1, 2^{2+1},2^n + 1}
(December 2014),
4th International Symposium on Integrated Circuits (ISIC), 10-12 December 2014, Singapore
[Conference Paper]
C. Chen, S.D. Cotofana,
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs
(December 2014),
7th International Workshop on Network on Chip Architectures (NoCArc 2014), 13-17 December 2014, Cambridge, UK
[Conference Paper]
T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana,
Towards Energy Effective LDPC Decoding by Exploiting Channel Noise Variability
(October 2014),
22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2014), 6-8 October 2014, Playa del Carmen, Mexico
[Conference Paper]
S. Grandhi, C. Spagnol, J. Chen, E. Popovici, S.D. Cotofana,
Reliability Aware Logic Synthesis through Rewriting
(September 2014),
27th International IEEE SoC (System-on-Chip) Conference (SOCC), 2-5 September, Las Vegas, USA
[Conference Paper]
J. Chen, E. Popovici, A. Tisserand, S.D. Cotofana,
Robust Sub-Powered Asynchronous Logic
(September 2014),
International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2014), 29 September - 1 October 2014, Palma de Mallorca, Spain
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Probability Density Function Based Reliability Evaluation of Large-Scale ICs
(July 2014),
10th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2014), 8-10 July 2014, Paris, France
[Conference Paper]
C. Chen, S.D. Cotofana,
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs
(July 2014),
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), 9-11 July 2014, Tampa, USA
[Conference Paper]
M. Lefter, M. Enachescu, G.R. Voicu, S.D. Cotofana,
Energy Effective 3D Stacked Hybrid NEMFET-CMOS Caches
(July 2014),
10th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2014), 8-10 July 2014, Paris, France
[Conference Paper]
J. Chen, C. Spagnol, S. Grandhi, E. Popovici, A. Amaricai, S.D. Cotofana,
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits
(July 2014),
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), 9-11 July 2014, Tampa, USA
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Critical Transistors Nexus Based Circuit-Level Aging Assessment and Prediction
(June 2014),
Journal of Parallel and Distributed Computing, volume 74, issue 6
[Journal Paper]
Y. Wang, S.D. Cotofana, L. Fang,
Analysis of the Impact of Spatial and Temporal Variation on the Stability of SRAM Arrays and Mitigation Technique Using Independent-Gate Devices
(June 2014),
Journal of Parallel and Distributed Computing, volume 74, issue 6
[Journal Paper]
H. Pettenghi, S.D. Cotofana, L.A. Sousa,
Efficient Method for Designing Modulo {2n ± k} Multipliers
(January 2014),
Journal of Circuits, Systems and Computers, volume 23, issue 1
[Journal Paper]
N. Aymerich, S.D. Cotofana, A. Rubio,
Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell based Architectures
(November 2013),
IEEE Transactions on Nanotechnology (TNANO), volume 12, issue 6
[Journal Paper]
N. Cucu Laurenciu, S.D. Cotofana,
A Direct Measurement Scheme of Amalgamated Aging Effects with Novel On-Chip Sensor
(October 2013),
21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2013), 7-9 October 2013, Istanbul, Turkey
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
A Nonlinear Degradation Path Dependent End-of-Life Estimation Framework from Noisy Observations
(September 2013),
Microelectronics Reliability, volume 53, issue 9-11
[Journal Paper]
C. Chen, S.D. Cotofana,
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs
(September 2013),
16th Euromicro Conference on Digital System Design (DSD 2013), 4-6 September 2013, Santander, Spain
[Conference Paper]
C. Chen, S.D. Cotofana,
A Low Cost Method to Tolerate Soft Errors in the NoC Router Control Plane
(September 2013),
26th Annual IEEE International SoC Conference (SOCC 2013), 4-6 September 2013, Erlangen, Germany
[Conference Paper]
G.R. Voicu, S.D. Cotofana,
Towards Heterogenous 3D-Stacked Reliable Computing with von Neumann Multiplexing
(July 2013),
9th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2013), July 15-17, 2013, New York City, USA
[Conference Paper]
G.R. Voicu, M. Lefter, M. Enachescu, S.D. Cotofana,
3D Stacked Wide-Operand Adders: A Case Study
(June 2013),
24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington D.C., USA
[Conference Paper]
C Bira, L Gugu, R Hobincu, V Codreanu, L Petrica, S.D. Cotofana,
An Energy Effective SIMD Accelerator for Visual Pattern Matching
(June 2013),
4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2013), 13-14 June 2013, Edinburgh, Scotland
[Conference Paper]
L Petrica, V Codreanu, S.D. Cotofana,
VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling
(June 2013),
12th IEEE Low Voltage Low Power Conference (FTFC 2013), 20-21 June 2013, Paris, France
[Conference Paper]
E.K. Bankas, K.A. Gbolagade, S.D. Cotofana,
An Effective New CRT Based Reverse Converter for a Novel Moduli Set { 2^(2n+1)-1, 2^(2n+1), 2^(2n)-1 }
(June 2013),
24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington D.C., USA
[Conference Paper]
Y. Wang, S.D. Cotofana, L. Fang,
Lifetime Reliability Assessment with Aging Information from Low-Level Sensors
(May 2013),
Great Lakes Symposium on VLSI (GLSVLSI 2013 ), 2-3 May 2013, Paris, France
[Conference Paper]
M. Enachescu, M. Lefter, A. Bazigos, A. Ionescu, S.D. Cotofana,
Ultra Low Power NEMFET Based Logic
(May 2013),
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
[Conference Paper]
M. Lefter, G.R. Voicu, M. Taouil, M. Enachescu, S. Hamdioui, S.D. Cotofana,
Is TSV-based 3D Integration Suitable for Inter-die Memory Repair?
(March 2013),
Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France
[Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana,
Context Aware Slope Based Transistor-Level Aging Model
(October 2012),
Microelectronics Reliability, volume 52, issue 9-10
[Journal Paper]
A.T. Nelson, A.M. Molnos, A. Beyranvand Nejad, D. Mirzoyan, S.D. Cotofana, K.G.W. Goossens,
Embedded Computer Architecture Laboratory: A Hands-on Experience Programming Embedded Systems with Resource and Energy Constraints
(October 2012),
Workshop on Embedded and Cyber-Physical Systems Education (WESE 2012), 11 October 2012, Tampere, Finland
[Conference Paper]
G.R. Voicu, M. Enachescu, S.D. Cotofana,
A 3D Stacked High Performance Scalable Architecture for 3D Fourier Transform
(September 2012),
30th IEEE International Conference on Computer Design (ICCD 2012), 30 September - 3 October 2012, Montreal, Canada
[Conference Paper]
Y. Wang, M. Enachescu, S.D. Cotofana, L. Fang,
Variation tolerant on-chip degradation sensors for dynamic reliability management systems
(September 2012),
Microelectronics Reliability, volume 52, issue 9-10
[Journal Paper]
N. Aymerich, S.D. Cotofana, A. Rubio,
Degradation Stochastic Resonance (DSR) in AD-AVG Architectures
(August 2012),
12th IEEE Conference on Nanotechnology (IEEE NANO 2012), 20-23 August 2012, Birmingham, UK
, Best PhD Student Paper Award
[Conference Paper]
Y. Wang, S.D. Cotofana, L. Fang,
Statistical Reliability Analysis of NBTI Impact on FinFET SRAMs and Mitigation Technique Using Independent-Gate Devices
(July 2012),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands
[Conference Paper]
N. Aymerich, S.D. Cotofana, A. Rubio,
Adaptive Fault-Tolerant Architecture for Unreliable Technologies with Heterogenous Variability
(July 2012),
IEEE Transactions on Nanotechnology (TNANO), volume 11, issue 4
[Journal Paper]
N. Cucu Laurenciu, S.D. Cotofana,
A Markovian, Variation-Aware Circuit-Level Aging Model
(July 2012),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands
[Conference Paper]
S. Safiruddin, F. Peper, S.D. Cotofana,
Stigmergic Search with Single Electron Tunneling Technology based Memory Enhanced Hubs
(July 2012),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands
, Best PhD Student Paper Award
[Conference Paper]
S. Safiruddin, M. Lefter, D. Borodin, G.R. Voicu, S.D. Cotofana,
Zero-Performance-Overhead Online Fault Detection and Diagnosis in 3D Stacked Integrated Circuits
(July 2012),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands
[Conference Paper]
M. Enachescu, G.R. Voicu, S.D. Cotofana,
Is the Road Towards "Zero-Energy" Paved with NEMFET-based Power Management?
(May 2012),
IEEE International Symposium on Circuits and Systems (ISCAS 2012), 20-23 May 2012, Seoul, Korea
, Finalist for Best Paper Award for PhD Students
[Conference Paper]
C. Chen, Ye Lu, S.D. Cotofana,
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip
(May 2012),
6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2012), 9-11 May 2012, Lyngby, Denmark
[Conference Paper]
A.M. Molnos, A. Beyranvand Nejad, B.T. Nguyen, S.D. Cotofana, K.G.W. Goossens,
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms
(May 2012),
5th Workshop on Mapping of Applications to MPSoCs & 15th International Workshop on Software and Compilers for Embedded Systems (Map2MPSoC/SCOPES 2012), 15-16 May 2012, St. Goar, Germany
[Conference Paper]
S. Safiruddin, D. Borodin, M. Lefter, G.R. Voicu, S.D. Cotofana,
Is 3D Integration The Way to Future Dependable Computing Platforms?
(May 2012),
13th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM 2012), 24-26 May 2012, Brasov, Romania
[Conference Paper]
M. Enachescu, G.R. Voicu, S.D. Cotofana,
Leakage-enhanced 3D-Stacked NEMFET-based Power Management Architecture for Autonomous Sensors Systems
(October 2011),
15th International Conference on System Theory, Control and Computing (ICSTCC 2011), 14-16 October 2011, Sinaia, Romania
, Best Paper Award for PhD Students
[Conference Paper]
K.A. Gbolagade, G.R. Voicu, S.D. Cotofana,
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1}
(August 2011),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 19, issue 8
[Journal Paper]
D. Borodin, W. Siauw, S.D. Cotofana,
Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems
(July 2011),
International Conference on Embedded Computer Systems: Architectures, Models, and Simulations (SAMOS XI), 18-21 July 2011, Samos, Greece
[Conference Paper]
G.R. Voicu, M. Enachescu, S.D. Cotofana,
Towards "Zero-energy" using NEMFET-based Power Management for 3D Hybrid Stacked ICs
(June 2011),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), 8-9 June 2011, San Diego, USA
[Conference Paper]
Y. Wang, S.D. Cotofana,
A Unified Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits
(June 2011),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), 8-9 June 2011, San Diego, USA
[Conference Paper]
D. Andrade, A. Rubio, A. Calomarde, S.D. Cotofana,
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations
(May 2011),
IEEE International Symposium on Circuits and Systems (ISCAS 2011), 15-18 May, 2011, Rio de Janeiro, Brazil
[Conference Paper]
J.A. Ambrose, A.M. Molnos, A.T. Nelson, S.D. Cotofana, K.G.W. Goossens, B.H.H. Juurlink,
Composable Local Memory Organisation for Streaming Applications on Embedded MPSoCs
(May 2011),
ACM International Conference on Computing Frontiers (CF 2011), 3-5 May 2011, Ischia, Italy
[Conference Paper]
M. Enachescu, G.R. Voicu, S.D. Cotofana,
Advanced NEMS-based Power Management for 3D Stacked Integrated Circuits
(December 2010),
International Conference on Energy Aware Computing (ICEAC 2010), 16-18 December 2010, Cairo, Egypt
[Conference Paper]
Y. Wang, S.D. Cotofana,
A Novel Virtual Age Reliability Model for Time-toFailure Prediction
(October 2010),
IEEE International Integrated Reliability Workshop Final Report (IRW 2010), 17-21 October 2010, South Lake Tahoe, USA
[Conference Paper]
S. Timarchi, M. Fazlali, S.D. Cotofana,
A Unified Addition Structure for Moduli Set {2n-1, 2n, 2n+1} based on a Novel RNS Representation
(October 2010),
28th International Conference on Computer Design (ICCD 2010), 3-6 October 2010, Amsterdam, The Netherlands
[Conference Paper]
K.A. Gbolagade, G.R. Voicu, S.D. Cotofana,
Memoryless RNS-to-Binary Converters for the moduli set {2n+1-1,2n,2n-1}
(July 2010),
21st IEEE International Conference on Application Specific Systems Architectures, and Processors (ASAP 2010), 7-9 July 2010, Rennes, France
[Conference Paper]
K.A. Gbolagade, G.R. Voicu, S.D. Cotofana,
An Efficient FPGA Design of Reverse Converter for the Moduli Set {2n+2,2n+1,2n}
(July 2010),
6th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2010), 11-17 July 2010, Terrassa, Spain
[Conference Paper]
K.A. Gbolagade, R. Chaves, L.A. Sousa, S.D. Cotofana,
An Improved Reverse Converter for the {2^{2n+1}-1, 2^{n}, 2^{n}-1} Moduli Set
(June 2010),
IEEE International Symposium on Circuits and Systems (ISCAS 2010), 30 May - 2 June 2010, Paris, France
[Conference Paper]
A.M. Molnos, J.A. Ambrose, A.T. Nelson, R.A. Stefan, K.G.W. Goossens, S.D. Cotofana,
A Composable, Energy-Managed, Real-Time MPSOC Platform
(May 2010),
12th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM 2010), 20-22 May 2010, Brasov, Romania
[Conference Paper]
K.A. Gbolagade, R. Chaves, L.A. Sousa, S.D. Cotofana,
Residue-to-Binary Converters for the Moduli Set {2^{2n+1}-1, 2^{2n}, 2^{n}-1}
(December 2009),
2nd International Conference On Adaptive Science & Technology (ICAST09), 14-16 December 2009, Accra, Ghana
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
A Reverse Converter for the New 4-Moduli Set {2n+3,2n+2,2n+1,2n}
(December 2009),
16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS09), 13-19 December 2009, Yasmine Hammamet, Tunesia
[Conference Paper]
M. Enachescu, A.J. van Genderen, S.D. Cotofana, A. Ionescu, D. Tsamados,
Can SG-FET Replace FET In Sleep Mode Circuits?
(October 2009),
4th International ICST Conference on Nano-Networks (NANO-NET 2009), 18-20 October 2009, Luzern, Switzerland
[Conference Paper]
M. Enachescu, A.J. van Genderen, S.D. Cotofana,
Suspended Gate Field Effect Transistor Based Power Management - A 32-Bit Adder Case Study
(October 2009),
International Semiconductor Conference (CAS 2009), 12-14 October 2009, Sinaia, Romania
, Honorific Mention
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
Residue-to-Decimal Converters for Moduli Sets with Common Factors
(August 2009),
52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009), 2-5 August 2009, Cancun, Mexico
[Conference Paper]
I.O. Agbo, S. Safiruddin, S.D. Cotofana,
Implementable Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology
(July 2009),
9th IEEE Conference on Nanotechnology (IEEE-NANO 2009), 26-30 July 2009, Genoa, Italy
[Conference Paper]
B. Kuiper, S.D. Cotofana,
Adaptive Clock Scheduling for Pipelined Structures
(July 2009),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009), 30-31 July 2009, San Fransisco, USA
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
An O(n) Residue Number System to Mixed Radix Conversion Technique
(May 2009),
IEEE International Symposium on Circuits and Systems (ISCAS 2009), 24-27 May 2009, Taipei, Taiwan
[Conference Paper]
N.Z.B. Haron, S. Hamdioui, S.D. Cotofana,
Emerging Non-CMOS Nanoelectronic Devices - What Are They?
(January 2009),
4th IEEE International Conference of Nano/Micro Engineered & Molecular Systems (IEEE-NEMS 2009), 5-8 January 2009, Shenzhen, China
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
MRC Technique for RNS to Decimal Conversion Using the Moduli Set {2n + 2, 2n + 1, 2n}
(November 2008),
19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
An Efficient RNS to Binary Converter Using the Moduli Set {2n+1, 2n, 2n-1}
(November 2008),
XXIII Conference on Design of Circuits and Integrated Systems (DCIS 2008), 12-14 November 2008, Grenoble, France
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
Generalized Matrix Method for Efficient Residue to Decimal Conversion
(November 2008),
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008), 30 November - 3 December 2008, Macao, China
[Conference Paper]
A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven,
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors
(October 2008),
Journal of Signal Processing Systems (JSPS), volume 57, issue 2
[Journal Paper]
K.A. Gbolagade, S.D. Cotofana,
A residue to Binary Converter for the {2n+2,2n+1,2n} Moduli Set
(October 2008),
42nd Asilomar Conference on Signals, Systems and Computers, 26-29 October 2008, Pacific Grove, USA
[Conference Paper]
R.A. Stefan, S.D. Cotofana,
Bitstream Compression Techniques for Virtex 4 FPGAs
(September 2008),
18th International Conference on Field Programmable Logic and Applications (FPL 2008), 8-10 September 2008, Heidelberg, Germany
[Conference Paper]
S. Safiruddin, S.D. Cotofana, F. Peper, J. Lee,
Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology
(August 2008),
8th IEEE Conference on Nanothechnology (NANO 2008), 18-21 August 2008, Arlington, USA
[Conference Paper]
K.A. Gbolagade, S.D. Cotofana,
Residue Number System Operands to Decimal Conversion for 3-Moduli Sets
(August 2008),
51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2008), 10-13 August 2008, Knoxville, USA
[Conference Paper]
B.H.H. Juurlink, I. Antochi, D. Crisu, S.D. Cotofana,
GRAAL: A Framework for Low-Power 3D Graphics Accelerators
(July 2008),
IEEE Computer Graphics and Applications (CGA), volume 28, issue 4
[Journal Paper]
S. Safiruddin, S.D. Cotofana, F. Peper,
Single Electron Tunneling Delay Insensitive and Fluctuation Based Computation Paradigms and Circuits
(June 2008),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008), 12-13 June 2008, Anaheim, USA
[Conference Paper]
A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers,
Compositional, dynamic cache management for embedded chip multiprocessors
(March 2008),
Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany
[Conference Paper]
F. Martorell, S.D. Cotofana, A. Rubio,
An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates
(January 2008),
IEEE Transactions on Nanotechnology (TNANO), volume 7, issue 1
[Journal Paper]
D. Lampridis, S.D. Cotofana,
High speed reconfigurable computation for electronic instrumentation in space applications
(November 2007),
18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands
[Conference Paper]
S.D. Cotofana,
On Effective Computation with Single Electron Devices
(November 2007),
22nd Conference on Design of Circuits and Integrated Systems (DCIS 2007), 21-23 November 2007, Sevilla, Spain
[Conference Paper]
F. Martorell, S.D. Cotofana, A. Rubio,
Manufacturability Issues of Redundant Nanogates
(October 2007),
International Semiconductor Conference (CAS 2007), 15-17 October 2007, Sinaia, Romania
[Conference Paper]
K.L.M. Bertels, S.D. Cotofana, G.N. Gaydadjiev, K.G.W. Goossens, S. Hamdioui, B.H.H. Juurlink, A.J. van Genderen, S. Wong,
The Future of Computing, essays in memory of Stamatis Vassiliadis
(September 2007),
Published by Computer Engineering Laboratory, TU Delft
[Book]
A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven,
Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors
(August 2007),
Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC), volume 1
[Journal Paper]
F. Martorell, S.D. Cotofana, A. Rubio,
Fault Tolerant Structures for Nanoscale Gates
(August 2007),
7th IEEE International Conference on Nanotechnology (IEEE-NANO 2007), 2-5 August 2007, Hong Kong, China
[Conference Paper]
S. Safiruddin, S.D. Cotofana,
Building Blocks for Delay-Insensitive Circuits using Single Electron Tunneling Devices
(August 2007),
7th IEEE International Conference on Nanotechnology (IEEE-NANO 2007), 2-5 August 2007, Hong Kong, China
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Computing Division Using Single-Electron Tunneling Technology
(July 2007),
IEEE Transactions on Nanotechnology (TNANO), volume 6, issue 4
[Journal Paper]
C.H. Meenderinck, S.D. Cotofana,
An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology
(March 2007),
Romanian Journal of Information Science and Technology (ROMJIST), volume 10, issue 1
[Journal Paper]
I. Koryfidis, S.D. Cotofana,
A Power Aware HW/SW Partitioning for a DVB-H Receiver Module
(November 2006),
17th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006), 23-24 November 2006, Veldhoven, The Netherlands
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Hierarchical Continuous Intelligence Simulation
(September 2006),
Romanian Journal of Information Science and Technology (ROMJIST)
[Journal Paper]
D. Milosavljevic, S.D. Cotofana,
A Method to Analyze the Fault Tolerance of Molecular Quantum-Dot Cellular Automata Systems
(September 2006),
International Semiconductor Conference (CAS 2006), 27-29 September 2006, Sinaia, Romania
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Basic Building Blocks for Effective Single Electron Tunneling Technology Based Computation
(September 2006),
International Semiconductor Conference (CAS 2006), 27-29 September 2006, Sinaia, Romania
[Conference Paper]
A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven,
Throughput Optimization via Cache Partitioning for Embedded Multiprocessors
(July 2006),
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), 17-20 July 2006, Samos, Greece
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology
(July 2006),
6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), 17-20 July 2006, Samos, Greece
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Computing Division in the Electron Counting Paradigm using Single Electron Tunneling Technology
(July 2006),
6th IEEE Conference on Nanotechnology (IEEE-NANO 2006), 17-20 July 2006, Cincinnati, USA
[Conference Paper]
A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven,
Static Cache Partitioning Robustness Analysis for Embedded OnChip MultiProcessors
(May 2006),
3rd International Conference on Computing Frontiers (CF 2006), 3-5 May 2006, Ischia, Italy
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Electron Counting based High-Radix Multiplication in Single Electron Tunneling Technology
(May 2006),
International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Kos, Greece
[Conference Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional, efficient caches for a chip multi-processor
(March 2006),
Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany
[Conference Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Inter-task sharing data and instructions in cache with enabling compositionality in parallel embedded systems
(November 2005),
16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands
[Conference Paper]
L. Zhang, S.D. Cotofana,
An Input Weights Aware Synthesis Tool for Threshold Logic Networks
(November 2005),
16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands
[Conference Paper]
K.C. Li, M.D. Padure, S.D. Cotofana,
neuronMOS enhanced Differential Current-Switch Threshold Logic Gates
(November 2005),
16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Periodic Symmetric Functions and Addition Related Arithmetic Operations in Single Electron Tunneling Technology
(November 2005),
16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands
[Conference Paper]
C.H. Meenderinck, S.D. Cotofana,
Computing Periodic Symmetric Functions in Single Electron Tunneling Technology
(October 2005),
International Semiconductor Conference (CAS 2005), 3-5 October 2005, Sinaia, Romania
, Best Paper Award
[Conference Paper]
S.D. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio,
CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures
(July 2005),
16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece
[Conference Paper]
C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana,
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology
(July 2005),
16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece
[Conference Paper]
C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana,
Design Methodology for Single Electron Based Building Blocks
(July 2005),
5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Buffer Design Trade-Offs for Single Electron Logic Gates
(July 2005),
5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan
, Best Paper Award
[Conference Paper]
M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis, L.J. Visser,
IEEE-Compliant IDCT on FPGA-Augmented TriMedia
(March 2005),
Journal of Signal Processing Systems (JSPS), volume 39, issue 3
[Journal Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional memory systems for multimedia communicating tasks
(March 2005),
Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany
[Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis,
Addition Related Arithmetic Operations via Controlled Transport of Charge
(March 2005),
IEEE Transactions on Computers (TC), volume 54, issue 3
[Journal Paper]
C. Hu, S.D. Cotofana, J. Jianfei,
Single-Electron Tunneling Transistor Implementation of Periodic Symmetric Functions
(November 2004),
IEEE Transactions on Circuits and Systems Part II: Express Briefs (TCAS), volume 51, issue 11
[Journal Paper]
C. Hu, S.D. Cotofana, J. Jianfei, Q. Cai,
Analog-to-Digital Converter Based on Single-Electron Tunneling Transistors
(November 2004),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 12, issue 11
[Journal Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Cache Partitioning Options for Compositional Multimedia Applications
(November 2004),
15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
3D Graphics Tile-Based Systolic Scan-Conversion
(November 2004),
38th Asilomar Conference on Signals, Systems and Computers (Asilomar 2004), 7-10 November 2004, Pacific Grove, USA
[Conference Paper]
A.J. van Genderen, S.D. Cotofana, G. de Graaf, A. Kaichouhi, J. Liedorp, R. Nouta, M.A.P. Pertijs, C.J.M. Verhoeven,
A CMOS Semi-Custom Chip for Mixed Signal Designs
(November 2004),
15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands
[Conference Paper]
L. Huang, D. Crisu, S.D. Cotofana,
Heuristic Algorithms for Primitive Traversal Acceleration in Tile-Based Rasterizers
(November 2004),
15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
Efficient Hardware for Tile-Based Rasterization
(November 2004),
15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands
[Conference Paper]
T. Niculiu, A. Manolescu, S.D. Cotofana,
Looking for Intelligent Reconfigurable Simulation
(October 2004),
European Simulation and Modelling Conference (ESMc 2004), 25-27 October 2004, Paris, France
[Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis,
On Effective Computation with Nanodevices: A single Electron Tunneling Case Study
(October 2004),
International Semiconductor Conference (CAS 2004), 4-6 October 2004, Sinaia, Romania
, Invited Paper
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
Determining a coverage mask for a pixel
(October 2004),
filed in USA
[Patent]
C. Hu, S.D. Cotofana, J. Jianfei,
Digital to analogue converter based on single-electron tunnelling transistor
(October 2004),
IEE Proceedings - Circuits, Devices and Systems, volume 151, issue 5
[Journal Paper]
P. Celinski, D. Abbott, S.D. Cotofana,
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
(September 2004),
14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), 15-17 September 2004, Santorini, Greece
[Conference Paper]
J. Cheng, C. Hu, S.D. Cotofana, J. Jianfei,
SPICE Implementation of a Compact Single Electron Tunneling Transistor Model
(August 2004),
4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany
[Conference Paper]
C. Hu, S.D. Cotofana, J. Jianfei,
Compact Current and Current Noise Models for Single-Electron Tunneling Transistors
(August 2004),
4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Binary Addition based on Single Electron Tunneling Devices
(August 2004),
4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
Logic-Enhanced Memory for 3D Graphics Tile-Based Rasterizers
(July 2004),
47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), 25-28 July 2004, Hiroshima, Japan
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Hierarchical Inteligent Simulation
(July 2004),
16th International Conference on Systems Research, Informatics and Cybernetics, 28 July - 4 August 2004, Baden-Baden, Germany
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
High-Level Energy Estimation for ARM-Based SOCs
(July 2004),
4th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2004), 19-21 July 2004, Samos, Greece
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
Efficient Hardware for Antialiasing Coverage Mask Generation
(June 2004),
Computer Graphics International Conference (CGI 2004), 16-19 June 2004, Crete, Greece
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Single Electron Encoded Latches and Flip-Flops
(June 2004),
IEEE Transactions on Nanotechnology (TNANO), volume 3, issue 2
[Journal Paper]
M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, L.J. Visser,
Pel Reconstruction on FPGA-Augmented TriMedia
(June 2004),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 12, issue 6
[Journal Paper]
C. Hu, S.D. Cotofana, J. Jianfei,
Analysis of Analog to Digital Converter Based on Single Electron Tuneling Transistors
(May 2004),
IEEE International Symposium on Circuits and Systems (ISCAS 2004), 23-26 May 2004, Vancouver, Canada
[Conference Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
Embedded Processors: Characteristics and Trends
(May 2004),
CE technical report
[Technical Report]
D. Crisu, S. Vassiliadis, S.D. Cotofana, P. Liuha,
Low Cost and Latency Embedded 3D Graphics Reciprocation
(May 2004),
IEEE International Symposium on Circuits and Systems (ISCAS 2004), 23-26 May 2004, Vancouver, Canada
[Conference Paper]
T. Niculiu, M. Ciuc, S.D. Cotofana,
Hierarchical Models for Intelligent Reconfigurable Simulation
(March 2004),
15th IASTED International Conference on Modelling and Simulation (MS 2004), 1-3 March 2004, Marina del Rey, USA
[Conference Paper]
P. Celinski, S.F. Al-Sarawi, D. Abbott, S.D. Cotofana, S. Vassiliadis,
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach
(February 2004),
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 19-20 February 2004, Lafayette, USA
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
GRAAL - A Development Framework for Embedded Graphics Accelerators
(February 2004),
Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France
[Conference Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional Memory Systems for Data Intensive Applications
(February 2004),
Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France
[Conference Paper]
T. Niculiu, C. Aktouf, S.D. Cotofana,
Hierarchical Testability Assisted Intelligent Simulation
(January 2004),
International Journal of Modelling and Simulation, volume 24, issue 1
[Journal Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
Future Directions of Programmable and Reconfigurable Embedded Processors
(January 2004),
Book Title "Domain-Specific Processors: Systems, Architectures, Modeling and Simulation", Published by Marcel Dekker Inc.
[Book Chapter]
T. Niculiu, S.D. Cotofana,
Hierarchical Templates for Simulated Intelligence
(December 2003),
Simulation News Europe (SNE), issue 38/39
[Journal Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates
(December 2003),
International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC 2003), 1-3 December 2003, Darmstadt, Germany
[Conference Paper]
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, B. Mesman,
Data Cache Optimization in Multimedia Applications
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Building Blocks for Electron Counting Arithmetic
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Single Electron Encoded SET Memory Elements
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven,
Inverse Quantization on FPGA-augmented TriMedia
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott,
Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
Design Tradeoffs for an Embedded OpenGL-Compliant Hardware Rasterizer
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
P.T. Stathis, S. Vassiliadis, S.D. Cotofana,
D-SAB: A Sparse Matrix Benchmark Suite
(September 2003),
7th International Conference on Parallel Computing Technologies (PaCT 2003), 15-19 September 2003, Novosibirsk, Russia
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha,
High-Level Energy Estimation for ARM-Based SOCs
(July 2003),
3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece
[Conference Paper]
S. Vassiliadis, S. Wong, S.D. Cotofana,
Microcode Processing: Positioning and Directions
(July 2003),
IEEE Micro, volume 23, issue 4
[Journal Paper]
M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven,
Color Space Conversion for MPEG Decoding on FPGA-augmented TriMedia Processor
(June 2003),
14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands
[Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott,
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder
(June 2003),
7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Hierarchical Reconfigurable Simulated Intelligence Templates
(June 2003),
IASTED International Conference on Intelligent Systems and Control (ISC 2003), 25–27 June 2003, Salzburg, Austria
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis,
CMOS Implementation of Generalized Threshold Functions
(June 2003),
7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain
[Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis,
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge
(June 2003),
16th IEEE Symposium on Computer Arithmetic (ARITH-16 2003), 15-18 June 2003, Santiago de Compostela, Spain
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis,
Design and Experimental Results of a CMOS Flip-Flop Featuring Embedded Threshold Logic
(May 2003),
International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand
[Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott,
Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic
(May 2003),
International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand
[Conference Paper]
P. Celinski, S.D. Cotofana, J.F. Lopez, S.F. Al-Sarawi, D. Abbott,
State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications
(May 2003),
SPIE International Symposium on Microtechnologies for the New Millennium, 19-21 May 2003, San Agustín, Gran Canaria, Spain
, Invited Paper
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Concurrent Engineering for Intelligent Simulation
(April 2003),
European Concurrent Engineering Conference (ECEC 2003), 14-16 April 2003, Plymouth, UK
[Conference Paper]
P.T. Stathis, S. Vassiliadis, S.D. Cotofana,
A Hierarchical Sparse Matrix Storage Format for Vector Processors
(April 2003),
17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France
[Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott,
Threshold Logic Parallel Counters for 32-bit Multipliers
(December 2002),
International Symposium on Smart Materials, Nano- and Micro-Smart Systems, 2-4 December 2002, Melbourne, Australia
[Conference Paper]
S. Wong, B. Stougie, S.D. Cotofana,
Alternatives in FPGA-based SAD Implementations
(December 2002),
1st IEEE International Conference on Field-Programmable Technology (FPT 2002), 16-18 December 2002, Hong Kong, China
[Conference Paper]
S. Wong, B. Stougie, S.D. Cotofana,
An Investigation on FPGA Based SAD Hardware Implementations
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis,
High-speed Hybrid Threshold-Boolean Logic
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis,
A CMOS Flip-flop Featuring Embedded Threshold Logic Functions
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis,
A Hardware/Software Co-Simulation Environment For Graphics Accelerator Development in ARM-based SOCs
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
W. Zwart, J. Eilers, G.N. Gaydadjiev, S.D. Cotofana,
DAMP - Delft Altera-based multimedia platform
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
M. Sima, S. Vassiliadis, J.T.J. van Eijndhoven, S.D. Cotofana,
YUV-to-RGB Color Space Conversion on FPGA-augmented TriMedia-32 Processor
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
S. Wong, G. Luo, S.D. Cotofana,
Synthetic Benchmark Generator for the MOLEN Processor
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
P.T. Stathis, S. Vassiliadis, S.D. Cotofana,
Design considerations of a multiple inner product and accumulate vector functional unit
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
A family of single electron static buffered Boolean logic
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
7/3 and 7/2 Counters implemented in single electron technology
(November 2002),
13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands
[Conference Paper]
T. Niculiu, C. Aktouf, S.D. Cotofana,
High-level intelligence-oriented simulation
(October 2002),
International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania
[Conference Paper]
M.D. Padure, S.D. Cotofana, C. Dan, S. Vassiliadis, M. Bodea,
Compact Delay Modeling of Latch-based Threshold Logic Gates
(October 2002),
International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania
, Best Paper Award
[Conference Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
A Sum of Absolute Differences Implementation in FPGA Hardware
(September 2002),
28th EUROMICRO Conference (EUROMICRO 2002), 4-6 September 2002, Dortmund, Germany
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, C. Dan, M. Bodea,
A low-power threshold logic family
(September 2002),
9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia
[Conference Paper]
M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, K.A. Vissers,
Field-Programmable Custom Computing Machines - A Taxonomy
(September 2002),
12th International Conference on Field-Programmable Logic and Applications (FPL 2002), 2-4 September 2002, Montpellier, France
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
A full adder implementation using SET based linear threshold gates
(September 2002),
9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia
[Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis,
High-speed hybrid threshold-Boolean logic counters
(August 2002),
45th Midwest Symposium on Circuits and Systems (MWSCAS 2002), 4-7 August 2002, Tulsa, USA
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Static buffered SET based logic gates
(August 2002),
2nd IEEE Conference on Nanotechnology (IEEE-NANO 2002), 26-28 August 2002, Washington DC, USA
[Conference Paper]
S. Wong, S.D. Cotofana,
On Teaching Embedded Systems Design to Electrical Engineering Students
(July 2002),
3rd International Conference on Information Communication Technologies in Education (ICICTE 2002), 17-19 July 2002, Samos, Greece
[Conference Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
Future Directions of (Programmable and Reconfigurable) Embedded Processors
(July 2002),
2nd International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), 22-25 July 2002, Samos, Greece
[Conference Paper]
M. Sima, E.J. Pol, J.T.J. van Eijndhoven, S.D. Cotofana, S. Vassiliadis,
Entropy Decoding on TriMedia/CPU64
(July 2002),
2nd International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), 22-25 July 2002, Samos, Greece
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Hierarchical Intellignet Mixed Simulation
(June 2002),
16th European Simulation Multiconference: Modelling and Simulation (ESM 2002), 3-5 June 2002, Darmstadt, Germany
[Conference Paper]
I. Lemberski, M. Koegst, S.D. Cotofana, B.H.H. Juurlink,
FSM Non-minimal state encoding for low power
(May 2002),
23rd International Conference on Microelectronics, 12-15 May 2002, Nis, Yugoslavia
[Conference Paper]
S.D. Cotofana, P.T. Stathis, S. Vassiliadis,
Direct and transposed sparse matrix-vector multiplication
(April 2002),
4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy
[Conference Paper]
M. Sima, S.D. Cotofana, S. Vassiliadis,
MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64
(April 2002),
10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002 , Napa, USA
[Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis,
A proposal of a tile-based open GL compliant rasterization engine
(January 2002),
CE technical report
[Technical Report]
D. Crisu, S.D. Cotofana, S. Vassiliadis,
An energy-aware architectural exploration tool for ARM-based SOCs
(November 2001),
12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
SAD Implementation in FPGA Hardware
(November 2001),
12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
P.T. Stathis, S.D. Cotofana, S. Vassiliadis,
Sparse Matrix Vector Multiplication Evaluation Using the BBCS scheme
(November 2001),
8th Panhellenic Conference on Informatics , 8-10 November 2001, Nicosia, Cyprus
[Conference Paper]
P.T. Stathis, S. Vassiliadis, S.D. Cotofana,
Transposition Mechanism for sparse matrices on vector processors
(November 2001),
12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven,
Variable-Length Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit
(November 2001),
12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Single electron encoded logic circuits
(November 2001),
4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
A turnstile based single electron memory element
(November 2001),
4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Achieving fanout capabilities in single electron encoded logic networks
(October 2001),
6th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2001), 22-25 October 2001, Shanghai, China
[Conference Paper]
M.D. Padure, S.D. Cotofana, C. Dan, M. Bodea, S. Vassiliadis,
A new latch-based threshold logic family
(October 2001),
International Semiconductor Conference (CAS 2001), 9-13 October 2001, Sinaia, Romania
[Conference Paper]
M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis,
An 8-point IDCT Computing Resource Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit
(October 2001),
2nd Workshop on Embedded Systems (PROGRESS 2001), 18 October 2001, Veldhoven, The Netherlands
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
Digital to analog conversion performed in single electron technology
(October 2001),
1st IEEE Conference on Nanotechnology (IEEE-NANO 2001), 28-30 October 2001, Maui, USA
[Conference Paper]
M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, K.A. Vissers,
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor
(September 2001),
19th International Conference on Computer Design (ICCD 2001), 23-26 September 2001, Austin, USA
[Conference Paper]
T. Niculiu, C. Aktouf, S.D. Cotofana,
MultiHierarchical Intelligent Simulation
(August 2001),
Polytechnical University of Bucharest Scientific Bulletin, Series C: Electrical Engineering, volume 63, issue 3-4
[Journal Paper]
S. Vassiliadis, S. Wong, S.D. Cotofana,
The MOLEN pu-coded Processor
(August 2001),
11th International Conference on Field-Programmable Logic and Applications (FPL 2001), 27-29 August 2001, Belfast, UK
[Conference Paper]
M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, K.A. Vissers,
A Reconfigurable Functional Unit for TriMedia/CPU64: A Case Study
(July 2001),
1st International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2001), 16–18 July 2001, Samos, Greece
[Conference Paper]
S. Wong, S. Vassiliadis, S.D. Cotofana,
Microcoded Reconfigurable Embedded Processors: Current Developments
(July 2001),
1st International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2001), 16–18 July 2001, Samos, Greece
[Conference Paper]
S. Vassiliadis, S. Wong, S.D. Cotofana,
Network Processors: Issues and Prospectives
(June 2001),
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2001), 25-28 June 2001, Las Vegas, USA
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Hierarchical intelligent simulation
(June 2001),
15th European Simulation Multiconference (ESM 2001), 6-9 June 2001, Prague, Czech Republic
[Conference Paper]
E. Moscu Panainte, I. Athanasiu, S.D. Cotofana,
An Optimization Framework for Retargetable Compilers
(May 2001),
13th International Conference on Control Systems and Computer Sciences (CSCS 2001), May 2001, Bucharest, Romania
[Conference Paper]
S.D. Cotofana, S. Wong, S. Vassiliadis,
Embedded Processors: Characteristics and Trends
(May 2001),
7th Annual Conference of the Advanced School for Computing and Imaging (ASCI 2001), 30 May - 1 June 2001, Heijen, The Netherlands
[Conference Paper]
T. Niculiu, S.D. Cotofana,
Multi-hierarchical learning-based co-simulation
(May 2001),
IASTED International Conference on Modelling and Simulation (MS 2001), 16-18 May 2001, Pittsburg, USA
[Conference Paper]
M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis, K.A. Vissers,
An 8x8 IDCT Implementation on an FPGA-augmented TriMedia
(April 2001),
9th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2001), 29 April - 2 May 2001, Rohnert Park, USA
[Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis,
A linear threshold gate implementation in single electron technology
(April 2001),
IEEE Computer Society Workshop on VLSI (WVLSI 2001), 19-20 April 2001, Orlando, USA
[Conference Paper]
S. Wong, S.D. Cotofana, S. Vassiliadis,
Coarse Reconfigurable Multimedia Unit Extension
(February 2001),
9th Euromicro Workshop on Parallel and Distributed Processing (PDP 2001), 7-9 February 2001, Mantova, Italy
[Conference Paper]
S. Vassiliadis, S. Wong, S.D. Cotofana,
The MOLEN pu-coded Processor
(January 2001),
CE technical report
[Technical Report]
M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, K.A. Vissers,
1st Workshop on Embedded Systems
(October 2000),
1st Workshop on Embedded Systems (PROGRESS 2000), 13 October 2000, Utrecht, The Netherlands
[Conference Paper]
T. Niculiu, S.D. Cotofana, A. Manolescu,
Hierarchical approach for hardware/software systems
(October 2000),
23rd International Semicondutor Conference (CAS 2000), 10-14 October 2000, Sinaia, Romania
[Conference Paper]
S.D. Cotofana, B.H.H. Juurlink, S. Vassiliadis,
Counter Based Superscalar Instruction Issuing
(September 2000),
26th EUROMICRO 2000 Conference, Informatics: Inventing the Future (EUROMICRO 2000), 5-7 September 2000, Maastricht, The Netherlands
[Conference Paper]
S. Vassiliadis, S.D. Cotofana, P.T. Stathis,
BBCS based sparse matrix-vector multiplication: initial evaluation
(August 2000),
16th IMACS World Congress on Scientific Computation, Applied Mathematics and Simulation (IMACS 2000), 21-25 August 2000, Lausanne, Switzerland
[Conference Paper]
M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis,
Hashed Addressed Caches for Embedded Pointer Based Codes
(August 2000),
6th International Euro-Par Conference on Parallel Processing (Euro-Par 2000), 29 August - 1 September 2000, Munich, Germany
[Conference Paper]
S. Wong, S.D. Cotofana, S. Vassiliadis,
Multimedia Enhanced General-Purpose Processors
(July 2000),
IEEE International Conference on Multimedia and Expo (ICME 2000), 30 July - 2 August 2000, New York, USA
[Conference Paper]
S. Vassiliadis, S.D. Cotofana, P.T. Stathis,
Block Based Compression Storage Expected Performance
(June 2000),
14th International Conference on High Performance Computing Systems and Applications (HPCS 2000), 14-17 June 2000, Victoria, Canada
[Conference Paper]
T. Niculiu, C. Aktouf, S.D. Cotofana,
Hierarchical interfaces for hardware/software systems
(May 2000),
14th European Simulation Multiconference - Simulation and Modelling: Enablers for a Better Quality of Life (ESM 2000), 23-26 May 2000, Ghent, Belgium
[Conference Paper]
S.D. Cotofana, S. Vassiliadis,
Signed digit addition and related operations with threshold logic
(March 2000),
IEEE Transactions on Computers (TC), volume 49, issue 3
[Journal Paper]
S. Wong, S.D. Cotofana, S. Vassiliadis,
General-Purpose Processor Huffman Encoding Extension
(March 2000),
International Conference on Information Technology: Coding and Computing (ITCC 2000), 27-29 March 2000, Las Vegas, USA
[Conference Paper]
M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis,
Array Based Structure Loop Transformations for Cache Miss Reduction
(February 2000),
18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria
[Conference Paper]
A. Berlea, S.D. Cotofana, I. Athanasiu, C.J. Glossner, S. Vassiliadis,
Garbage collection for the Delft Java Processor
(February 2000),
18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria
[Conference Paper]