Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, A memory specific notation for fault modeling (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Simulation based analysis of temperature effect on the faulty behaviour of embedded DRAMs (October 2001), IEEE International Test Conference (ITC 2001), 30 October - 1 November 2001, Baltimore, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, B. Gauch, D. Richter, W. Spirkl, Development of a DRAM simulation model for fault analysis purposes (February 2001), 13th Workshop on Testmethods and Reliability of Circuits and Systems, 18–20 February 2001, Miesbach, Germany [Conference Paper]