Z. Al-Ars

NameZ. Al-Ars
First NameZaid
E-mailZ.Al-Ars@tudelft.nl
Author TypeStaff
AffiliationTU Delft

Publications

E.J. Houtgast, V.M. Sima, Z. Al-Ars, High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL (to appear: October 2017), 17th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2017), 23-25 October 2017, Washington DC, USA , full paper [Conference Paper]
M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Transition Fault Testing for Offline Adaptive Voltage Scaling (to appear: October 2017), International Test Conference (ITC 2017), 31 October - 2 November 2017, Fort Worth, USA [Conference Proceedings]
H. Mushtaq, Z. Al-Ars, P Hofstee, SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale (to appear: August 2017), 8th ACM Conference on Bioinformatics, Computational Biology and Health Informatics (ACM-BCB 2017), 20-23 August 2017, Boston, USA [Conference Paper]
J.W. Peltenburg, A.S. Hesam, Z. Al-Ars, Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware? (to appear: June 2017), International Workshop on OpenPOWER for HPC (IWOPH17), 22 June 2017, Frankfurt, Germany [Conference Paper]
Y. Ma, G Smaragdos, Z. Al-Ars, C. Strydis, Towards Real-Time Whisker Tracking in Rodents for Studying Sensorimotor Disorders 1626_towards_realtime_whisker_tracking_in_rodents_for_studying.pdf (July 2017), International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII (2017)), 17-20 July 2017, Samos, Greece [Conference Paper]
M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Using Transition Fault Test Patterns for Cost Effective Offline Performance Estimation (April 2017), 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain [Conference Paper]
J.J. Hoozemans, R.W. Heij, J. Van Straten, Z. Al-Ars, VLIW-based FPGA computational fabric with streaming memory hierarchy for medical imaging applications 1602_vliwbased_fpga_computational_fabric_with_streaming_memory.pdf (April 2017), 13th International Symposium on Applied Reconfigurable Computing (ARC2017), 3-7 April 2017, Delft, The Netherlands [Conference Paper]
M. Zandrahimi, A. Castillejo, P. Debaud, Z. Al-Ars, Industrial Approaches for Performance Evaluation Using On-Chip Monitors 1561_industrial_approaches_for_performance_evaluation_using_onc.pdf (December 2016), 11th IEEE International Design & Test Symposium (IDT 2016), 18-20 December 2016, Hammamet, Tunisia [Conference Paper]
E.J. Houtgast, V.M. Sima, G. Marchiori, K.L.M. Bertels, Z. Al-Ars, Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms 1549_powerefficiency_analysis_of_accelerated_bwamem_implementa.pdf (December 2016), International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016), 30 November - 2 December 2016, Cancun, Mexico , full paper [Conference Paper]
N. Ahmed, K.L.M. Bertels, Z. Al-Ars, A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms 1597_a_comparison_of_seedandextend_techniques_in_modern_dna_re.pdf (December 2016), Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics (WACEBI 2016), 15 December 2016, Shenzhen, China [Conference Paper]
J.W. Peltenburg, S. Ren, Z. Al-Ars, Maximizing Systolic Array Efficiency to Accelerate the PairHMM Forward Algorithm 1596_maximizing_systolic_array_efficiency_to_accelerate_the_pair.pdf (December 2016), IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2016), 15-18 December 2016, Shenzhen, China [Conference Paper]
S. Ren, K.L.M. Bertels, Z. Al-Ars, Exploration of Alternative GPU Implementations of the Pair-HMMs Forward Algorithm 1562_exploration_of_alternative_gpu_implementations_of_the_pair.pdf (December 2016), 3rd International Workshop on High Performance Computing on Bioinformatics (HPCB 2016), 15-18 December 2016, Shenzhen, China [Conference Paper]
E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM 1536_an_efficient_gpuaccelerated_implementation_of_genomic_shor.pdf (July 2016), International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2016), 25-27 July 2016, Hong Kong, China , full paper [Conference Paper]
E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, Computational Challenges of Next Generation Sequencing Pipelines Using Heterogeneous Systems 1535_computational_challenges_of_next_generation_sequencing_pipe.pdf (July 2016), 12th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2016), 10-16 July 2016, Fiuggi, Italy , abstract only [Conference Proceedings]
E.J. Houtgast, V.M. Sima, G. Marchiori, K.L.M. Bertels, Z. Al-Ars, Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms 1531_powerefficient_accelerated_genomic_short_read_mapping_on_h.pdf (May 2016), 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016), 1-3 May 2016, Washington DC, USA , abstract only [Conference Paper]
E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing 1520_gpuaccelerated_bwamem_genomic_mapping_algorithm_using_ada.pdf (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany [Conference Paper]
V.V. Kritchallo, B. Braithwaite, E. Vermij, K.L.M. Bertels, Z. Al-Ars, Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector 1526_balancing_highperformance_parallelization_and_accuracy_in.pdf (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany [Conference Paper]
M. Zandrahimi, Z. Al-Ars, P. Debaud, A. Castillejo, Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation (March 2016), Design, Automation and Test in Europe (DATE 2016), 14-18 March 2016, Dresden, Germany [Conference Proceedings]
V.V. Kritchallo, E. Vermij, K.L.M. Bertels, Z. Al-Ars, Fidelity Slider: a User-Defined Method to Trade off Accuracy for Performance in Canny Edge Detector 1530_fidelity_slider_a_userdefined_method_to_trade_off_accurac.pdf (January 2016), 11th HiPEAC conference (HiPEAC 2016), 18-20 January 2016, Prague, Czech Republic , online publication [Conference Paper]
S. Ren, V.M. Sima, Z. Al-Ars, FPGA Acceleration of the Pair-HMMs Forward Algorithm for DNA Sequence Analysis 1525_fpga_acceleration_of_the_pairhmms_forward_algorithm_for_dn.pdf (November 2015), International Workshop on High Performance Computing on Bioinformatics (HPCB 2015), 9-12 November 2015, Washington DC, USA [Conference Paper]
H. Mushtaq, Z. Al-Ars, Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline 1523_clusterbased_apache_spark_implementation_of_the_gatk_dna_a.pdf (November 2015), IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2015), 9-12 November 2015, Washington DC, USA [Conference Proceedings]
N. Ahmed, V.M. Sima, E.J. Houtgast, K.L.M. Bertels, Z. Al-Ars, Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm 1500_heterogeneous_hardwaresoftware_acceleration_of_the_bwamem.pdf (November 2015), International Conference On Computer Aided Design (ICCAD 2015), 2-6 November 2015, Austin, USA [Conference Paper]
C. Pham-Quoc, I. Ashraf, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators with Hybrid Interconnect: an Automated Design Approach 1498_heterogeneous_hardware_accelerators_with_hybrid_interconnec.pdf (November 2015), International Conference on Advanced Computing and Applications (ACOMP 2015), 23-25 November 2015, Ho Chi Minh City, Vietnam [Conference Proceedings]
Z. Al-Ars, H. Mushtaq, Scalability Potential of BWA DNA Mapping Algorithm on Apache Spark 1495_scalability_potential_of_bwa_dna_mapping_algorithm_on_apach.pdf (September 2015), 2nd Annual International Symposium on Information Management and Big Data (SIMBig 2015), 2-4 September 2015, Cusco, Peru [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Calculation of Worst-Case Execution Time for Multicore Processors using Deterministic Execution 1494_calculation_of_worstcase_execution_time_for_multicore_proc.pdf (September 2015), 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2015), 1-4 September 2015, Salvador, Brazil [Conference Proceedings]
E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, An FPGA-Based Systolic Array to Accelerate the BWA-MEM Genomic Mapping Algorithm 1499_an_fpgabased_systolic_array_to_accelerate_the_bwamem_geno.pdf (September 2015), International Conference On Embedded Computer Systems: Architectures, Modeling, And Simulation (SAMOS XV (2015)), 20-23 July 2015, Samos, Greece [Conference Paper]
J.J. Hoozemans, S. Wong, Z. Al-Ars, Using VLIW Softcore Processors for Image Processing Applications 1506_using_vliw_softcore_processors_for_image_processing_applica.pdf (July 2015), International Conference On Embedded Computer Systems: Architectures, Modeling, And Simulation (SAMOS XV (2015)), 20-23 July 2015, Samos, Greece [Conference Paper]
H.A. Du Nguyen, Z. Al-Ars, G Smaragdos, C. Strydis, Accelerating complex brain-model simulations on GPU platforms 1475_accelerating_complex_brainmodel_simulations_on_gpu_platfor.pdf (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]
M. Zandrahimi, Z. Al-Ars, A Survey on Low-Power Techniques for Single and Multicore Systems 1449_a_survey_on_lowpower_techniques_for_single_and_multicore_s.pdf (October 2014), 3rd International Conference on Context-Aware Systems and Applications (ICCASA 2014), 15-16 October 2014, Dubai, United Arab Emirates [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling 1437_automated_hybrid_interconnect_design_for_fpga_accelerators.pdf (May 2014), 28th International Parallel & Distributed Processing Symposium Workshops (IPDPSW 2014), 19-23 May 2014, Phoenix, USA [Conference Paper]
Z. Al-Ars, K.L.M. Bertels, E. Cuppen, Integrated Approach to Whole Genome Diagnostics 1431_integrated_approach_to_whole_genome_diagnostics.pdf (April 2014), Netherlands Bioinformatics Conference (NBIC 2014), 8-9 April 2014, Lunteren, the Netherlands [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Accurate and Efficient Identification of Worst-Case Execution Time for Multicore Processors: A Survey 1400_accurate_and_efficient_identification_of_worstcase_executi.pdf (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
Z. Al-Ars, Reducing Random-Dopant Fluctuation Impact on Core-Speed and Power Variability in Many-Core Platforms (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
M. Zandrahimi, Z. Al-Ars, An Overview of Power Reduction Techniques for Single and Multicore Systems 1433_an_overview_of_power_reduction_techniques_for_single_and_mu.pdf (November 2013), ICT.OPEN 2013, 27-28 November 2013, Eindhoven, The Netherlands [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing 1387_heterogeneous_hardware_accelerator_architecture_for_streami.pdf (October 2013), International Conference on Advanced Technologies for Communications (ATC 2013), 16-18 October 2013, Hochiminh City, Vietnam [Conference Paper]
J. de Sonneville, K.-J. van der Kolk, W. Veneman, R. Lodder, Z. Al-Ars, H. Spaink, Analysing RNA-seq data using GeneTiles 1432_analysing_rnaseq_data_using_genetiles.pdf (July 2013), European Zebrafish Meeting (EZM 2013), 9-13 July 2013, Bercelona, Spain [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators Interconnect: An Overview 1371_heterogeneous_hardware_accelerators_interconnect_an_overvi.pdf (June 2013), NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), 25-27 June 2013, Torino, Italy [Conference Paper]
C. Pham-Quoc, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker, K.L.M. Bertels, Hybrid Interconnect Design for Heterogeneous Hardware Accelerators 1324__hybrid_interconnect_design_for_heterogeneous_hardware__acc.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Efficient Software Based Fault Tolerance Approach on Multicore Platforms 1321_efficient_software_based_fault_tolerance_approach_on_multic.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators Interconnect: An Overview 1335_heterogeneous_hardware_accelerators_interconnect_an_overvi.pdf (January 2013), 7th HiPEAC Workshop on Reconfigurable Computing (WRC 2013), 21 January 2013, Berlin, Germany [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Rule-Based Data Communication Optimization Using Quantitative Communication Profiling 1224_rulebased_data_communication_optimization_using_quantitati.pdf (December 2012), International Conference on Field-Programmable Technology (FPT 2012), 10-12 December 2012, Seoul, Korea [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, A Heuristic-based Communication-aware Hardware Optimization Approach in Heterogeneous Multicore Systems 1316_a_heuristicbased_communicationaware_hardware_optimization.pdf (December 2012), International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), 5-7 December 2012, Cancun, Mexico [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Fault Tolerance on Multicore processors using Deterministic Multithreading 1322_fault_tolerance_on_multicore_processors_using_deterministic.pdf (November 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems 1311_detlock_portable_and_efficient_deterministic_execution_for.pdf (November 2012), 5th International Workshop on Multi-Core Computing Systems (MuCoCoS 2012), 16 November 2012, Salt Lake City, USA [Conference Paper]
M. Shahsavari, Z. Al-Ars, K.L.M. Bertels, Evaluation of Different Task Scheduling Policies in Multi-Core Systems with Reconfigurable Hardware 1295_evaluation_of_different_task_scheduling_policies_in_multic.pdf (July 2012), 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2012), 8-14 July 2012, Fiuggi, Italy [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, A User-level Library for Fault Tolerance on Shared Memory Multicore Systems 135_a_userlevel_library_for_fault_tolerance_on_shared_memory_mu.pdf (April 2012), 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), 18-20 April 2012, Tallinn, Estonia [Conference Paper]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Survey of Fault Tolerance Techniques for Shared Memory Multicore/Multiprocessor Systems 94_survey_of_fault_tolerance_techniques_for_shared_memory_multic.pdf (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]
Z. Al-Ars, A New Test Paradigm for Semiconductor Memories in the Nano-Era (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Testing for Parasitic Memory Effect in SRAMs 99_testing_for_parasitic_memory_effect_in_srams.pdf (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
L. Hasan, Z. Al-Ars, An Overview of Hardware-Based Acceleration of Biological Sequence Alignment 7_computational_biology_and_applied_bioinformatics.pdf (September 2011), Book Title "Computational Biology and Applied Bioinformatics", Published by InTech [Book Chapter]
L. Hasan, M.A. Kentie, Z. Al-Ars, GPU-Accelerated Protein Sequence Alignment 18_gpuaccelerated_protein_sequence_alignment.pdf (August 2011), 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2011), 30 August - 3 September 2011, Boston, USA [Conference Paper]
L. Hasan, M.A. Kentie, Z. Al-Ars, DOPA: GPU-based Protein Alignment Using Database and Memory Access Optimizations 40_dopa_gpubased_protein_alignment_using_database_and_memory_a.pdf (July 2011), BMC Research Notes, volume 4, issue 261 [Journal Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs 61_memory_test_optimization_for_parasitic_bit_line_coupling_in_s.pdf (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell, Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs 71_influence_of_parasitic_memory_effect_on_singlecell_faults_in.pdf (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]
L. Hasan, Z. Al-Ars, M. Taouil, K.L.M. Bertels, Performance and Bandwidth Optimization for Biological Sequence Alignment 236_performance_and_bandwidth_optimization_for_biological_sequen.pdf (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Detecting Memory Faults in the Presence of Bit Line Coupling in SRAM Devices 248_detecting_memory_faults_in_the_presence_of_bit_line_coupling.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
Z. Al-Ars, INDEXYS, a Logical Step beyond GENESYS (September 2010), Lecture Notes in Computer Science (LNCS), volume 6351 [Journal Paper]
L. Hasan, Z. Al-Ars, M. Taouil, High Performance and Resource Efficient Biological Sequence Alignment 151_high_performance_and_resource_efficient_biological_sequence.pdf (September 2010), 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2010), 31 August - 4 September 2010, Buenos Aires, Argentina [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs 202_bit_line_coupling_memory_tests_for_singlecell_fails_in_sram.pdf (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]
I.S. Irobi, Z. Al-Ars, Worst-Case Bit Line Coupling Backgrounds for Open Defects in SRAM Cells 396_worstcase_bit_line_coupling_backgrounds_for_open_defects_in.pdf (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]
Z. Al-Ars, S. Hamdioui, Non-Algorithmic Stress Optimization Using Simulation for DRAMs 394_nonalgorithmic_stress_optimization_using_simulation_for_dra.pdf (November 2009), 4th International Design and Test Workshop (IDT 2009), 15-17 November 2009, Riyadh, Saudi Arabia [Conference Paper]
Z. Al-Ars, S. Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories 393_fault_diagnosis_using_test_primitives_in_random_access_memor.pdf (November 2009), 18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan [Conference Paper]
L. Hasan, Z. Al-Ars, Performance Comparison between Linear RVE and Linear Systolic Array Implementations of the Smith-Waterman Algorithm 389_performance_comparison_between_linear_rve_and_linear_systoli.pdf (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]
L. Hasan, Z. Al-Ars, An Efficient and High Performance Linear Recursive Variable Expansion Implementation of the Smith-Waterman Algorithm 288_an_efficient_and_high_performance_linear_recursive_variable.pdf (September 2009), 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2009), 2-6 September 2009, Minneapolis, USA [Conference Paper]
M. Imran, Z. Al-Ars, G.N. Gaydadjiev, Improving Soft Error Correction Capability of 4-D Parity Codes 348_improving_soft_error_correction_capability_of_4d_parity_cod.pdf (May 2009), 14th IEEE European Test Symposium (ETS 2009), 25-29 May 2009, Sevilla, Spain [Conference Paper]
S. Hamdioui, Z. Al-Ars, Scan More with Memory Scan Test 355_scan_more_with_memory_scan_test.pdf (April 2009), 4th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2009), 6-9 April 2009, Cairo, Egypt [Conference Paper]
Z. Al-Ars, S. Hamdioui, Evaluation of SRAM Faulty Behavior Under Bit Line Coupling 516_evaluation_of_sram_faulty_behavior_under_bit_line_coupling.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
S. Hamdioui, Z. Al-Ars, Efficient Tests and DFT for RAM Address Decoder Delay Faults 515_efficient_tests_and_dft_for_ram_address_decoder_delay_faults.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
L. Hasan, Z. Al-Ars, Z. Nawaz, K.L.M. Bertels, Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion 512_hardware_implementation_of_the_smithwaterman_algorithm_usin.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
K. Yamasaki, S. Hamdioui, Z. Al-Ars, A.J. van Genderen, G.N. Gaydadjiev, High Quality Simulation Tool for Memory Redundancy Algorithms 535_high_quality_simulation_tool_for_memory_redundancy_algorithm.pdf (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]
L. Hasan, Z. Al-Ars, Z. Nawaz, A Novel Approach for Accelerating the Smith-Waterman Algorithm using Recursive Variable Expansion 533_a_novel_approach_for_accelerating_the_smithwaterman_algorit.pdf (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, BIST Enhancement for Detecting Bit/Byte Write Enable Faults in SOC SRAMs 526_bist_enhancement_for_detecting_bitbyte_write_enable_faults.pdf (November 2008), IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller, Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs 545_defect_oriented_testing_of_the_strap_problem_under_process_v.pdf (October 2008), IEEE International Test Conference (ITC 2008), 26-31 October 2008, Santa Clara, USA [Conference Paper]
Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Smith-Waterman Using Recursive Variable Expansion 425_acceleration_of_smithwaterman_using_recursive_variable_expa.pdf (September 2008), 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2008), 3-5 September 2008, Parma, Italy [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, S. Vassiliadis, Test Set Development for Cache Memory in Modern Microprocessors 471_test_set_development_for_cache_memory_in_modern_microprocess.pdf (June 2008), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 16, issue 6 [Journal Paper]
L. Hasan, Z. Al-Ars, Accurate Profiling and Acceleration Evaluation of the Smith-Waterman Algorithm using the MOLEN Platform 490_accurate_profiling_and_acceleration_evaluation_of_the_smith.pdf (April 2008), IADIS International Conference on Applied Computing (AC 2008), 10-13 April 2008, Algarve, Portugal [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Precise Identification of Memory Faults Using Electrical Simulation 647_precise_identication_of_memory_faults_using_electrical_si.pdf (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, An Investigation on Capacitive Coupling in RAM Address Decoders 641_an_investigation_on_capacitive_coupling_in_ram_address_decod.pdf (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]
S.B. Kootkar, Z. Al-Ars, Design and Implementation of Reliable Wireless Sensor Networks - A Case Study in Commuter Trains 685_design_and_implementation_of_reliable_wireless_sensor_networ.pdf (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]
L. Hasan, Z. Al-Ars, Performance Improvement of the Smith-Waterman Algorithm 668_performance_improvement_of_the_smithwaterman_algorithm.pdf (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]
Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Biological Sequence Alignment using Recursive Variable Expansion 645_acceleration_of_biological_sequence_alignment_using_recursiv.pdf (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]
Z. Al-Ars, S. Hamdioui, Automatic Analysis of Memory Faulty Behavior in Defective Memories 686_automatic_analysis_of_memory_faulty_behavior_in_defective_me.pdf (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Paper]
L. Hasan, Z. Al-Ars, S. Vassiliadis, Hardware Acceleration of Sequence Alignment Algorithms - An Overview 562_hardware_acceleration_of_sequence_alignment_algorithms__an.pdf (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Optimizing Test Length for Soft Faults in DRAM Devices 621_optimizing_test_length_for_soft_faults_in_dram_devices.pdf (May 2007), 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, PPM Reduction on Embedded Memories in System on Chip 615_ppm_reduction_on_embedded_memories_in_system_on_chip.pdf (May 2007), 12th IEEE European Test Symposium (ETS 2007), 20-24 May 2007, Freiburg, Germany [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices 628_manifestation_of_precharge_faults_in_high_speed_dram_devices.pdf (April 2007), 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2007), 11-13 April 2007, Krakow, Poland [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs 771_influence_of_bit_line_coupling_and_twisting_on_the_faulty_be.pdf (December 2006), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12 [Journal Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder 768_opens_and_delay_faults_in_cmos_ram_address_decoder.pdf (December 2006), IEEE Transactions on Computers (TC), volume 55, issue 12 [Journal Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Using Linear Tests for Transient Faults in DRAMs 789_using_linear_tests_for_transient_faults_in_drams.pdf (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]
E.B. Tunçer, Z. Al-Ars, E. Akar, J. Beintema, I.S. Sariyildiz, DesignMap: Capturing Design Knowledge in Architectural Practice 792_designmap_capturing_design_knowledge_in_architectural_pract.pdf (November 2006), Joint International Conference on Construction Culture, Innovation and Management (CCIM 2006), 26-29 November 2006, Dubai, UAE [Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Comparison of Static and Dynamic Faults in 65nm Memory Technology 790_comparison_of_static_and_dynamic_faults_in_65nm_memory_techn.pdf (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev, J. Vollrath, DRAM-Specific Space of Memory Tests 798_dramspecific_space_of_memory_tests.pdf (October 2006), IEEE International Test Conference (ITC 2006), 22-27 October 2006, Santa Clara, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, L. Mhamdi, G.N. Gaydadjiev, Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies 708_trends_in_tests_and_failure_mechanisms_in_deep_submicron_te.pdf (September 2006), International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006), 5-7 September 2006, Tunis, Tunesia [Conference Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, J. Vollrath, Bitline-Coupled Precharge Faults and Their Detection in Memory Devices 748_bitlinecoupled_precharge_faults_and_their_detection_in_memo.pdf (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies 747_investigation_of_singlecell_dynamic_faults_in_deepsubmicro.pdf (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Space of DRAM Fault Models and Corresponding Testing 761_space_of_dram_fault_models_and_corresponding_testing.pdf (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany [Conference Paper]
Z. Al-Ars, S. Hamdioui, J. Vollrath, Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach 862_investigations_of_faulty_dram_behavior_using_electrical_simu.pdf (December 2005), 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R. Wadsworth, Impact of Stresses on the Fault Coverage of Memory Tests 819_impact_of_stresses_on_the_fault_coverage_of_memory_tests.pdf (August 2005), IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan [Conference Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor, Framework for Fault Analysis and Test Generation in DRAMs 857_framework_for_fault_analysis_and_test_generation_in_drams.pdf (March 2005), Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany [Conference Paper]
S. Hamdioui, J.D. Reyes, Z. Al-Ars, Evaluation of Intra-Word Faults in Word-Oriented RAMs 966_evaluation_of_intraword_faults_in_wordoriented_rams.pdf (November 2004), 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan [Conference Paper]
Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs 911_influence_of_bit_line_twisting_on_the_faulty_behavior_of_dra.pdf (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants 912_the_effectiveness_of_scan_test_and_its_new_variants.pdf (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens 936_tests_for_address_decoder_delay_faults_in_rams_due_to_inter.pdf (May 2004), 9th IEEE European Test Symposium (ETS 2004), 23-26 May 2004, Corsica, France [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results 931_linked_faults_in_random_access_memories_concept_fault_mode.pdf (May 2004), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 23, issue 5 [Journal Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs 944_effects_of_bit_line_coupling_on_the_faulty_behavior_of_drams.pdf (April 2004), 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Soft Faults and the Importance of Stresses in Memory Testing 954_soft_faults_and_the_importance_of_stresses_in_memory_testing.pdf (February 2004), Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces 1068_analyzing_the_impact_of_process_variations_on_dram_testing.pdf (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, March SL: A Test For All Static Linked Memory Faults 1065_march_sl_a_test_for_all_static_linked_memory_faults.pdf (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Test generation and optimization for DRAM cell defects using electrical simulation 1082_test_generation_and_optimization_for_dram_cell_defects_usin.pdf (October 2003), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 22, issue 10 [Journal Paper]
Z. Al-Ars, A.J. van de Goor, Systematic memory test generation for dram defects causing two floating nodes 1024_systematic_memory_test_generation_for_dram_defects_causing.pdf (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs 1021_a_fault_primitive_based_analysis_of_linked_faults_in_rams.pdf (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests 1039_dynamic_faults_in_randomaccessmemories_concept_fault_mo.pdf (April 2003), Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2 [Journal Paper]
Z. Al-Ars, A.J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs 1046_static_and_dynamic_behavior_of_memory_cell_array_spot_defec.pdf (March 2003), IEEE Transactions on Computers (TC), volume 52, issue 3 [Journal Paper]
Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation 1044_optimizing_stresses_for_testing_dram_cell_defects_using_ele.pdf (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]
Z. Al-Ars, A.J. van de Goor, DRAM Specific approximation of the faulty behavior of cell defects 1148_dram_specific_approximation_of_the_faulty_behavior_of_cell.pdf (November 2002), 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Approximating Infinite Dynamic Behavior for DRAM Cell Defects 1121_approximating_infinite_dynamic_behavior_for_dram_cell_defec.pdf (April 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Modeling techniques and tests for partial faults in memory devices 1127_modeling_techniques_and_tests_for_partial_faults_in_memory.pdf (March 2002), Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Testing static and dynamic faults in random access memories 1167_testing_static_and_dynamic_faults_in_random_access_memories.pdf (January 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, A memory specific notation for fault modeling 1225_a_memory_specific_notation_for_fault_modeling.pdf (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]
Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Simulation based analysis of temperature effect on the faulty behaviour of embedded DRAMs 1232_simulation_based_analysis_of_temperature_effect_on_the_faul.pdf (October 2001), IEEE International Test Conference (ITC 2001), 30 October - 1 November 2001, Baltimore, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Transient faults in DRAMs: concept, analysis and impact on tests 1181_transient_faults_in_drams_concept_analysis_and_impact_on.pdf (August 2001), 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs 1206_static_and_dynamic_behavior_of_memory_cell_array_opens_and.pdf (March 2001), Conference on Design, Automation and Test in Europe (DATE 2001), 12-16 March 2001, Munich, Germany [Conference Paper]
Z. Al-Ars, A.J. van de Goor, J. Braun, B. Gauch, D. Richter, W. Spirkl, Development of a DRAM simulation model for fault analysis purposes 1210_development_of_a_dram_simulation_model_for_fault_analysis_p.pdf (February 2001), 13th Workshop on Testmethods and Reliability of Circuits and Systems, 18–20 February 2001, Miesbach, Germany [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Impact of memory cell array bridges on the faulty behavior in embedded DRAMs 1276_impact_of_memory_cell_array_bridges_on_the_faulty_behavior.pdf (December 2000), 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan [Conference Paper]
A.J. van de Goor, Z. Al-Ars, Functional memory faults: a formal notation and a taxonomy 1264_functional_memory_faults_a_formal_notation_and_a_taxonomy.pdf (April 2000), 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada [Conference Paper]