S. Ren, N. Ahmed, K.L.M. Bertels, Z. Al-Ars, GPU Accelerated Sequence Alignment with Traceback for GATK HaplotypeCaller (January 2019), 17th Asia-Pacific Bioinformatics Conference (APBC 2019), 14-16 Januari 2019, Wuhan, China , accepted for publication in BMC Genomics 2019 [Conference Paper]

Z. Al-Ars, S. van der Vlugt, P. Jaaskelainen, F. van der Linden, ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications (November 2018), Journal of Signal Processing Systems (JSPS) [Journal Paper]

S. Ren, N. Ahmed, K.L.M. Bertels, Z. Al-Ars, An Efficient GPU-based de Bruijn Graph Construction Algorithm for Micro-Assembly (October 2018), 18th IEEE International Conference on BioInformatics and BioEngineering (BIBE 2018), 29-31 October 2018, Taichung, Taiwan [Conference Paper]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM (October 2018), 18th IEEE International Conference on BioInformatics and BioEngineering (BIBE 2018), 29-31 October 2018, Taichung, Taiwan [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing (September 2018), 16th IEEE East-West Design & Test Symposium (EWDTS 2018), 14-17 September 2018, Kazan, Russia [Conference Paper]

J. Fang, J. Chen, P. Hofstee, Z. Al-Ars, J. Hidders, A High-Bandwidth Snappy Decompressor in Reconfigurable Logic (September 2018), International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2018), 30 September - 5 October 2018, Torino, Italy [Conference Paper]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, Hardware Acceleration of BWA-MEM Genomic Short Read Mapping for Longer Read Lengths (August 2018), Computational Biology and Chemistry (Comput. Biol. Chem), volume 75 [Journal Paper]

J.J. Hoozemans, J. van Straten, Z. Al-Ars, S. Wong, Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors (April 2018), 31st International Conference on Architecture of Computing Systems (ARCS2018), 9-12 April 2018, Braunschweig, Germany [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Industrial Evaluation of Transition Fault Testing for Cost Effective Offline Adaptive Voltage Scaling (March 2018), Design, Automation and Test in Europe (DATE 2018), 19-23 March 2018, Dresden, Germany [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns (March 2018), Design, Automation and Test in Europe (DATE 2018), 19-23 March 2018, Dresden, Germany [Conference Paper]

J. Chen, Z. Al-Ars, P. Hofstee, A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using (Open)CAPI (March 2018), Conference for Next Generation Arithmetic (CoNGA), 28 March 2018, Sentosa, Singapore , CC-BY [Conference Paper]

S. Ren, K.L.M. Bertels, Z. Al-Ars, Efficient Acceleration of the Pair-HMMs Forward Algorithm for GATK HaplotypeCaller on GPUs (March 2018), Evolutionary Bioinformatics, volume 14 , CC BY-NC [Journal Paper]

P. Bhosale, M. Staring, Z. Al-Ars, F. Berendsen, GPU-Based Stochastic-Gradient Optimization for Non-Rigid Medical Image Registration in Time-Critical Applications (February 2018), SPIE Medical Imaging Conference, 10-15 February 2018, Houston (TX), United States [Conference Paper]

J.W. Peltenburg, A.S. Hesam, Z. Al-Ars, Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware? (November 2017), International Workshop on OpenPOWER for HPC (IWOPH17), 22 June 2017, Frankfurt, Germany [Conference Paper]

G Smaragdos, R. Kukreja, I. Sourdis, Z. Al-Ars, C. Kachris, D. Soudris, C. Strydis, BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations (November 2017), Journal of Neural Engineering (J NEURAL ENG), volume 14 [Journal Paper]

N. Ahmed, H. Mushtaq, K.L.M. Bertels, Z. Al-Ars, GPU Accelerated API for Alignment of Genomics Sequencing Data (November 2017), IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2017), 13-16 November 2017, Kansas City, USA [Conference Paper]

N. Ahmed, K.L.M. Bertels, Z. Al-Ars, Predictive Genome Analysis Using Partial DNA Sequencing Data (October 2017), 17th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2017), 23-25 October 2017, Washington DC, USA [Conference Paper]

S. Ren, K.L.M. Bertels, Z. Al-Ars, GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization (October 2017), 17th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2017), 23-25 October 2017, Washington DC, USA [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Transition Fault Testing for Offline Adaptive Voltage Scaling (October 2017), International Test Conference (ITC 2017), 31 October - 2 November 2017, Fort Worth, USA [Conference Paper]

H. Mushtaq, N. Ahmed, Z. Al-Ars, Streaming Distributed DNA Sequence Alignment Using Apache Spark (October 2017), 17th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2017), 23-25 October 2017, Washington DC, USA [Conference Paper]

E.J. Houtgast, V.M. Sima, Z. Al-Ars, High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL (October 2017), 17th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2017), 23-25 October 2017, Washington DC, USA , full paper [Conference Paper]

H. Mushtaq, Z. Al-Ars, P. Hofstee, SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale (August 2017), 8th ACM Conference on Bioinformatics, Computational Biology and Health Informatics (ACM-BCB 2017), 20-23 August 2017, Boston, USA [Conference Paper]

Y. Ma, G Smaragdos, Z. Al-Ars, C. Strydis, Towards Real-Time Whisker Tracking in Rodents for Studying Sensorimotor Disorders (July 2017), International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII (2017)), 17-20 July 2017, Samos, Greece [Conference Paper]

J.J. Hoozemans, R.W. Heij, J. van Straten, Z. Al-Ars, VLIW-based FPGA computational fabric with streaming memory hierarchy for medical imaging applications (April 2017), 13th International Symposium on Applied Reconfigurable Computing (ARC2017), 3-7 April 2017, Delft, The Netherlands [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Using Transition Fault Test Patterns for Cost Effective Offline Performance Estimation (April 2017), 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain [Conference Paper]

E.J. Houtgast, V.M. Sima, G. Marchiori, K.L.M. Bertels, Z. Al-Ars, Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms (December 2016), International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016), 30 November - 2 December 2016, Cancun, Mexico , full paper [Conference Paper]

N. Ahmed, K.L.M. Bertels, Z. Al-Ars, A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms (December 2016), Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics (WACEBI 2016), 15 December 2016, Shenzhen, China [Conference Paper]

J.W. Peltenburg, S. Ren, Z. Al-Ars, Maximizing Systolic Array Efficiency to Accelerate the PairHMM Forward Algorithm (December 2016), IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2016), 15-18 December 2016, Shenzhen, China [Conference Paper]

S. Ren, K.L.M. Bertels, Z. Al-Ars, Exploration of Alternative GPU Implementations of the Pair-HMMs Forward Algorithm (December 2016), 3rd International Workshop on High Performance Computing on Bioinformatics (HPCB 2016), 15-18 December 2016, Shenzhen, China [Conference Paper]

M. Zandrahimi, A. Castillejo, P. Debaud, Z. Al-Ars, Industrial Approaches for Performance Evaluation Using On-Chip Monitors (December 2016), 11th IEEE International Design & Test Symposium (IDT 2016), 18-20 December 2016, Hammamet, Tunisia [Conference Paper]

Z. Al-Ars, N. Ahmed, K.L.M. Bertels, Early DNA Analysis Using Incomplete DNA Datasets (November 2016), filed in Europe [Patent]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM (July 2016), International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2016), 25-27 July 2016, Hong Kong, China , Proceedings published in ACM SIGARCH Computer Architecture News (journal) [Conference Paper]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, Computational Challenges of Next Generation Sequencing Pipelines Using Heterogeneous Systems (July 2016), 12th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2016), 10-16 July 2016, Fiuggi, Italy , abstract only [Conference Proceedings]

E.J. Houtgast, V.M. Sima, G. Marchiori, K.L.M. Bertels, Z. Al-Ars, Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms (May 2016), 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016), 1-3 May 2016, Washington DC, USA , abstract only [Conference Paper]

V.V. Kritchallo, B. Braithwaite, E. Vermij, K.L.M. Bertels, Z. Al-Ars, Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany [Conference Paper]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany [Conference Paper]

M. Zandrahimi, P. Debaud, A. Castillejo, Z. Al-Ars, Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation (March 2016), Design, Automation and Test in Europe (DATE 2016), 14-18 March 2016, Dresden, Germany [Conference Paper]

V.V. Kritchallo, E. Vermij, K.L.M. Bertels, Z. Al-Ars, Fidelity Slider: a User-Defined Method to Trade off Accuracy for Performance in Canny Edge Detector (January 2016), 11th HiPEAC conference (HiPEAC 2016), 18-20 January 2016, Prague, Czech Republic , online publication [Conference Paper]

N. Ahmed, V.M. Sima, E.J. Houtgast, K.L.M. Bertels, Z. Al-Ars, Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm (November 2015), International Conference On Computer Aided Design (ICCAD 2015), 2-6 November 2015, Austin, USA [Conference Paper]

C. Pham-Quoc, I. Ashraf, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators with Hybrid Interconnect: an Automated Design Approach (November 2015), International Conference on Advanced Computing and Applications (ACOMP 2015), 23-25 November 2015, Ho Chi Minh City, Vietnam [Conference Proceedings]

H. Mushtaq, Z. Al-Ars, Cluster-Based Apache Spark Implementation of the GATK DNA Analysis Pipeline (November 2015), IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2015), 9-12 November 2015, Washington DC, USA [Conference Paper]

S. Ren, V.M. Sima, Z. Al-Ars, FPGA Acceleration of the Pair-HMMs Forward Algorithm for DNA Sequence Analysis (November 2015), International Workshop on High Performance Computing on Bioinformatics (HPCB 2015), 9-12 November 2015, Washington DC, USA [Conference Paper]

E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, An FPGA-Based Systolic Array to Accelerate the BWA-MEM Genomic Mapping Algorithm (September 2015), International Conference On Embedded Computer Systems: Architectures, Modeling, And Simulation (SAMOS XV (2015)), 20-23 July 2015, Samos, Greece [Conference Paper]

Z. Al-Ars, H. Mushtaq, Scalability Potential of BWA DNA Mapping Algorithm on Apache Spark (September 2015), 2nd Annual International Symposium on Information Management and Big Data (SIMBig 2015), 2-4 September 2015, Cusco, Peru [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Calculation of Worst-Case Execution Time for Multicore Processors using Deterministic Execution (September 2015), 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2015), 1-4 September 2015, Salvador, Brazil [Conference Paper]

J.J. Hoozemans, S. Wong, Z. Al-Ars, Using VLIW Softcore Processors for Image Processing Applications (July 2015), International Conference On Embedded Computer Systems: Architectures, Modeling, And Simulation (SAMOS XV (2015)), 20-23 July 2015, Samos, Greece [Conference Paper]

H.A. Du Nguyen, Z. Al-Ars, G Smaragdos, C. Strydis, Accelerating complex brain-model simulations on GPU platforms (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]

W. Veneman, J. de Sonneville, K.J. van der Kolk, A. Ordas, Z. Al-Ars, A.H. Meijer, H. Spaink, Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics (December 2014), Immunogenetics [Journal Paper]

M. Zandrahimi, Z. Al-Ars, A Survey on Low-Power Techniques for Single and Multicore Systems (October 2014), 3rd International Conference on Context-Aware Systems and Applications (ICCASA 2014), 15-16 October 2014, Dubai, United Arab Emirates [Conference Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling (May 2014), 28th International Parallel & Distributed Processing Symposium Workshops (IPDPSW 2014), 19-23 May 2014, Phoenix, USA [Conference Paper]

Z. Al-Ars, K.L.M. Bertels, E. Cuppen, Integrated Approach to Whole Genome Diagnostics (April 2014), Netherlands Bioinformatics Conference (NBIC 2014), 8-9 April 2014, Lunteren, the Netherlands [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Accurate and Efficient Identification of Worst-Case Execution Time for Multicore Processors: A Survey (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]

Z. Al-Ars, Reducing Random-Dopant Fluctuation Impact on Core-Speed and Power Variability in Many-Core Platforms (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]

M. Zandrahimi, Z. Al-Ars, An Overview of Power Reduction Techniques for Single and Multicore Systems (November 2013), ICT.OPEN 2013, 27-28 November 2013, Eindhoven, The Netherlands [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Efficient and Highly Portable Deterministic Multithreading (DetLock) (November 2013), Computing [Journal Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing (October 2013), International Conference on Advanced Technologies for Communications (ATC 2013), 16-18 October 2013, Hochiminh City, Vietnam [Conference Paper]

J. de Sonneville, K.J. van der Kolk, W. Veneman, R. Lodder, Z. Al-Ars, H. Spaink, Analysing RNA-seq data using GeneTiles (July 2013), European Zebrafish Meeting (EZM 2013), 9-13 July 2013, Bercelona, Spain [Conference Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators Interconnect: An Overview (June 2013), NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), 25-27 June 2013, Torino, Italy [Conference Paper]

S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, GENERIC MARCH ELEMENT BASED MEMORY BUILT-IN SELF TEST (April 2013), filed in USA [Patent]

C. Pham-Quoc, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker, K.L.M. Bertels, Hybrid Interconnect Design for Heterogeneous Hardware Accelerators (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Efficient Software Based Fault Tolerance Approach on Multicore Platforms (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerators Interconnect: An Overview (January 2013), 7th HiPEAC Workshop on Reconfigurable Computing (WRC 2013), 21 January 2013, Berlin, Germany [Conference Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, A Heuristic-based Communication-aware Hardware Optimization Approach in Heterogeneous Multicore Systems (December 2012), International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), 5-7 December 2012, Cancun, Mexico [Conference Paper]

C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Rule-Based Data Communication Optimization Using Quantitative Communication Profiling (December 2012), International Conference on Field-Programmable Technology (FPT 2012), 10-12 December 2012, Seoul, Korea [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems (November 2012), 5th International Workshop on Multi-Core Computing Systems (MuCoCoS 2012), 16 November 2012, Salt Lake City, USA [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Fault Tolerance on Multicore processors using Deterministic Multithreading (November 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Paper]

M. Shahsavari, Z. Al-Ars, K.L.M. Bertels, Evaluation of Different Task Scheduling Policies in Multi-Core Systems with Reconfigurable Hardware (July 2012), 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2012), 8-14 July 2012, Fiuggi, Italy [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, A User-level Library for Fault Tolerance on Shared Memory Multicore Systems (April 2012), 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), 18-20 April 2012, Tallinn, Estonia [Conference Paper]

H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Survey of Fault Tolerance Techniques for Shared Memory Multicore/Multiprocessor Systems (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]

Z. Al-Ars, A New Test Paradigm for Semiconductor Memories in the Nano-Era (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]

I.S. Irobi, Z. Al-Ars, S. Hamdioui, Testing for Parasitic Memory Effect in SRAMs (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]

L. Hasan, Z. Al-Ars, An Overview of Hardware-Based Acceleration of Biological Sequence Alignment (September 2011), Book Title "Computational Biology and Applied Bioinformatics", Published by InTech [Book Chapter]

L. Hasan, M.A. Kentie, Z. Al-Ars, GPU-Accelerated Protein Sequence Alignment (August 2011), 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2011), 30 August - 3 September 2011, Boston, USA [Conference Paper]

L. Hasan, M.A. Kentie, Z. Al-Ars, DOPA: GPU-based Protein Alignment Using Database and Memory Access Optimizations (July 2011), BMC Research Notes, volume 4, issue 261 [Journal Paper]

I.S. Irobi, Z. Al-Ars, S. Hamdioui, Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]

I.S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell, Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]

L. Hasan, Z. Al-Ars, M. Taouil, K.L.M. Bertels, Performance and Bandwidth Optimization for Biological Sequence Alignment (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]

I.S. Irobi, Z. Al-Ars, S. Hamdioui, Detecting Memory Faults in the Presence of Bit Line Coupling in SRAM Devices (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]

Z. Al-Ars, INDEXYS, a Logical Step beyond GENESYS (September 2010), Lecture Notes in Computer Science (LNCS), volume 6351 [Journal Paper]

L. Hasan, Z. Al-Ars, M. Taouil, High Performance and Resource Efficient Biological Sequence Alignment (September 2010), 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2010), 31 August - 4 September 2010, Buenos Aires, Argentina [Conference Paper]

I.S. Irobi, Z. Al-Ars, S. Hamdioui, Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]

L. Hasan, Z. Al-Ars, Performance Comparison between Linear RVE and Linear Systolic Array Implementations of the Smith-Waterman Algorithm (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]

I.S. Irobi, Z. Al-Ars, Worst-Case Bit Line Coupling Backgrounds for Open Defects in SRAM Cells (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]

Z. Al-Ars, S. Hamdioui, Non-Algorithmic Stress Optimization Using Simulation for DRAMs (November 2009), 4th International Design and Test Workshop (IDT 2009), 15-17 November 2009, Riyadh, Saudi Arabia [Conference Paper]

Z. Al-Ars, S. Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories (November 2009), 18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan [Conference Paper]

L. Hasan, Z. Al-Ars, An Efficient and High Performance Linear Recursive Variable Expansion Implementation of the Smith-Waterman Algorithm (September 2009), 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2009), 2-6 September 2009, Minneapolis, USA [Conference Paper]

M. Imran, Z. Al-Ars, G.N. Gaydadjiev, Improving Soft Error Correction Capability of 4-D Parity Codes (May 2009), 14th IEEE European Test Symposium (ETS 2009), 25-29 May 2009, Sevilla, Spain [Conference Paper]

S. Hamdioui, Z. Al-Ars, Scan More with Memory Scan Test (April 2009), 4th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2009), 6-9 April 2009, Cairo, Egypt [Conference Paper]

L. Hasan, Z. Al-Ars, Z. Nawaz, K.L.M. Bertels, Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]

Z. Al-Ars, S. Hamdioui, Evaluation of SRAM Faulty Behavior Under Bit Line Coupling (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]

S. Hamdioui, Z. Al-Ars, Efficient Tests and DFT for RAM Address Decoder Delay Faults (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]

K. Yamasaki, S. Hamdioui, Z. Al-Ars, A.J. van Genderen, G.N. Gaydadjiev, High Quality Simulation Tool for Memory Redundancy Algorithms (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]

L. Hasan, Z. Al-Ars, Z. Nawaz, A Novel Approach for Accelerating the Smith-Waterman Algorithm using Recursive Variable Expansion (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]

S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, BIST Enhancement for Detecting Bit/Byte Write Enable Faults in SOC SRAMs (November 2008), IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller, Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs (October 2008), IEEE International Test Conference (ITC 2008), 26-31 October 2008, Santa Clara, USA [Conference Paper]

Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Smith-Waterman Using Recursive Variable Expansion (September 2008), 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2008), 3-5 September 2008, Parma, Italy [Conference Paper]

Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, S. Vassiliadis, Test Set Development for Cache Memory in Modern Microprocessors (June 2008), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 16, issue 6 [Journal Paper]

L. Hasan, Z. Al-Ars, Accurate Profiling and Acceleration Evaluation of the Smith-Waterman Algorithm using the MOLEN Platform (April 2008), IADIS International Conference on Applied Computing (AC 2008), 10-13 April 2008, Algarve, Portugal [Conference Paper]

Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Precise Identification of Memory Faults Using Electrical Simulation (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]

S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, An Investigation on Capacitive Coupling in RAM Address Decoders (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]

S.B. Kootkar, Z. Al-Ars, Design and Implementation of Reliable Wireless Sensor Networks - A Case Study in Commuter Trains (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]

L. Hasan, Z. Al-Ars, Performance Improvement of the Smith-Waterman Algorithm (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]

Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Biological Sequence Alignment using Recursive Variable Expansion (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]

Z. Al-Ars, S. Hamdioui, Automatic Analysis of Memory Faulty Behavior in Defective Memories (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Paper]

L. Hasan, Z. Al-Ars, S. Vassiliadis, Hardware Acceleration of Sequence Alignment Algorithms - An Overview (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Paper]

S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, PPM Reduction on Embedded Memories in System on Chip (May 2007), 12th IEEE European Test Symposium (ETS 2007), 20-24 May 2007, Freiburg, Germany [Conference Paper]

Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Optimizing Test Length for Soft Faults in DRAM Devices (May 2007), 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, USA [Conference Paper]

Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices (April 2007), 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2007), 11-13 April 2007, Krakow, Poland [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs (December 2006), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12 [Journal Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder (December 2006), IEEE Transactions on Computers (TC), volume 55, issue 12 [Journal Paper]

E.B. Tunçer, Z. Al-Ars, E. Akar, J. Beintema, I.S. Sariyildiz, DesignMap: Capturing Design Knowledge in Architectural Practice (November 2006), Joint International Conference on Construction Culture, Innovation and Management (CCIM 2006), 26-29 November 2006, Dubai, UAE [Conference Paper]

S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Comparison of Static and Dynamic Faults in 65nm Memory Technology (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]

Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Using Linear Tests for Transient Faults in DRAMs (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev, J. Vollrath, DRAM-Specific Space of Memory Tests (October 2006), IEEE International Test Conference (ITC 2006), 22-27 October 2006, Santa Clara, USA [Conference Paper]

S. Hamdioui, Z. Al-Ars, L. Mhamdi, G.N. Gaydadjiev, Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies (September 2006), International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006), 5-7 September 2006, Tunis, Tunesia [Conference Paper]

Z. Al-Ars, S. Hamdioui, G. Mueller, J. Vollrath, Bitline-Coupled Precharge Faults and Their Detection in Memory Devices (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]

S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Space of DRAM Fault Models and Corresponding Testing (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany [Conference Paper]

Z. Al-Ars, S. Hamdioui, J. Vollrath, Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach (December 2005), 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R. Wadsworth, Impact of Stresses on the Fault Coverage of Memory Tests (August 2005), IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan [Conference Paper]

Z. Al-Ars, DRAM Fault Analysis and Test Generation (June 2005), [Phd Thesis]

Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor, Framework for Fault Analysis and Test Generation in DRAMs (March 2005), Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany [Conference Paper]

S. Hamdioui, J.D. Reyes, Z. Al-Ars, Evaluation of Intra-Word Faults in Word-Oriented RAMs (November 2004), 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan [Conference Paper]

A.J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]

Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]

A.J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens (May 2004), 9th IEEE European Test Symposium (ETS 2004), 23-26 May 2004, Corsica, France [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results (May 2004), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 23, issue 5 [Journal Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs (April 2004), 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Soft Faults and the Importance of Stresses in Memory Testing (February 2004), Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, March SL: A Test For All Static Linked Memory Faults (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Test generation and optimization for DRAM cell defects using electrical simulation (October 2003), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 22, issue 10 [Journal Paper]

Z. Al-Ars, A.J. van de Goor, Systematic memory test generation for dram defects causing two floating nodes (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests (April 2003), Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2 [Journal Paper]

Z. Al-Ars, A.J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs (March 2003), IEEE Transactions on Computers (TC), volume 52, issue 3 [Journal Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, DRAM Specific approximation of the faulty behavior of cell defects (November 2002), 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Approximating Infinite Dynamic Behavior for DRAM Cell Defects (April 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Modeling techniques and tests for partial faults in memory devices (March 2002), Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Testing static and dynamic faults in random access memories (January 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, A memory specific notation for fault modeling (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Simulation based analysis of temperature effect on the faulty behaviour of embedded DRAMs (October 2001), IEEE International Test Conference (ITC 2001), 30 October - 1 November 2001, Baltimore, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Transient faults in DRAMs: concept, analysis and impact on tests (August 2001), 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs (March 2001), Conference on Design, Automation and Test in Europe (DATE 2001), 12-16 March 2001, Munich, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, B. Gauch, D. Richter, W. Spirkl, Development of a DRAM simulation model for fault analysis purposes (February 2001), 13th Workshop on Testmethods and Reliability of Circuits and Systems, 18–20 February 2001, Miesbach, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Impact of memory cell array bridges on the faulty behavior in embedded DRAMs (December 2000), 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan [Conference Paper]

A.J. van de Goor, Z. Al-Ars, Functional memory faults: a formal notation and a taxonomy (April 2000), 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada [Conference Paper]