S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, GENERIC MARCH ELEMENT BASED MEMORY BUILT-IN SELF TEST (April 2013), filed in USA [Patent]

A.J. van de Goor, H. Kukner, S. Hamdioui, Optimizing Memory BIST Address Generator Implementations (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece , Best Paper Award [Conference Paper]

A.J. van de Goor, S. Hamdioui, H. Kukner, Generic, Orthogonal and Low-Cost March Element-based Memory BIST (January 2011), IEEE International Test Conference (IEEE ITC), 20-22 Sept, Anaheim, CA, USA [Conference Proceedings]

A.J. van de Goor, S. Hamdioui, MBIST Architecture Framework based on Orthogonal Constructs (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]

A.J. van de Goor, C. Jung, S. Hamdioui, G.N. Gaydadjiev, Low-cost, Customized and Flexible SRAM MBIST Engine (April 2010), 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria [Conference Paper]

A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev, Using a CISC microcontroller to test embedded memories (April 2010), 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria [Conference Paper]

A.J. van de Goor, G.N. Gaydadjiev, S. Hamdioui, Memory Testing with a RISC Microcontroller (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany [Conference Paper]

A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev, New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults (November 2009), 18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller, Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs (October 2008), IEEE International Test Conference (ITC 2008), 26-31 October 2008, Santa Clara, USA [Conference Paper]

S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, An Investigation on Capacitive Coupling in RAM Address Decoders (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs (December 2006), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12 [Journal Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder (December 2006), IEEE Transactions on Computers (TC), volume 55, issue 12 [Journal Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev, J. Vollrath, DRAM-Specific Space of Memory Tests (October 2006), IEEE International Test Conference (ITC 2006), 22-27 October 2006, Santa Clara, USA [Conference Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Space of DRAM Fault Models and Corresponding Testing (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany [Conference Paper]

S. Hamdioui, A.J. van de Goor, J.D. Reyes, M. Rodgers, Memory Test Experiment: Industrial Results and Data (January 2006), IEE Proceedings - Computers and Digital Techniques, volume 153, issue 1 [Journal Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R. Wadsworth, Impact of Stresses on the Fault Coverage of Memory Tests (August 2005), IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan [Conference Paper]

Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor, Framework for Fault Analysis and Test Generation in DRAMs (March 2005), Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany [Conference Paper]

A.J. van de Goor, S. Hamdioui, R. Wadsworth, Detecting Faults in Peripheral Circuits and an Evaluation of SRAM Tests (October 2004), International Test Conference (ITC 2004), 26-28 October 2004, Charlotte, USA [Conference Paper]

A.J. van de Goor, An industrial evaluation of DRAM tests (September 2004), IEEE Design & Test of Computers (D&ToC), volume 21, issue 5 [Journal Paper]

S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor, The State-of-the-art and Future Trends in Testing Embedded Memories (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]

A.J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]

Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]

S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor, Memory Fault Modeling Trends: A Case Study (June 2004), Journal of Electronic Testing: Theory and Applications (JETTA), volume 20, issue 3 [Journal Paper]

A.J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens (May 2004), 9th IEEE European Test Symposium (ETS 2004), 23-26 May 2004, Corsica, France [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results (May 2004), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 23, issue 5 [Journal Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs (April 2004), 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Soft Faults and the Importance of Stresses in Memory Testing (February 2004), Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]

S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor, A Fault Primitive Based Analysis of Dynamic Memory Faults (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, March SL: A Test For All Static Linked Memory Faults (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]

A.J. van de Goor, I.B.S. Tlili, A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories (October 2003), IEEE Transactions on Computers (TC), volume 52, issue 10 [Journal Paper]

Z. Al-Ars, A.J. van de Goor, Test generation and optimization for DRAM cell defects using electrical simulation (October 2003), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 22, issue 10 [Journal Paper]

Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Systematic memory test generation for dram defects causing two floating nodes (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]

S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor, Importance of Dynamic Faults for New SRAM Technologies (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]

A.J. van de Goor, Testing (embedded) memories : new fault models, test, Dft, BIST, BISR and industrial results (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]

M.J. Geuzebroek, A.J. van de Goor, TPI for improving PR Fault Coverage of Boolean and Three-State Circuits (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]

S. Hamdioui, A.J. van de Goor, M. Rodgers, Detecting intra-word faults in word-oriented memories (April 2003), 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, USA [Conference Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests (April 2003), Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2 [Journal Paper]

I. Schanstra, A.J. van de Goor, Consequences of RAM bitline twisting for test coverage (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs (March 2003), IEEE Transactions on Computers (TC), volume 52, issue 3 [Journal Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]

I. Schanstra, A.J. van de Goor, Logical and topological testing of scrambled RAMs (February 2003), 4th IEEE Latin American Test Workshop (LATW 2003), 16-19 February 2003, Natal, Brazil [Conference Paper]

A.J. van de Goor, Memory Testing (January 2003), Book Title "Testing of Digital Systems", Published by Cambridge University Press [Book Chapter]

A.J. van de Goor, Introduction (January 2003), Book Title "Testing of Digital Systems", Published by Cambridge University Press [Book Chapter]

Z. Al-Ars, A.J. van de Goor, DRAM Specific approximation of the faulty behavior of cell defects (November 2002), 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA [Conference Paper]

M.J. Geuzebroek, J. van der Linden, A.J. van de Goor, Test point insertion that facilitates ATPG in reducing test time and data volume (October 2002), IEEE International Test Conference (ITC 2002), 7-10 October 2002, Baltimore, USA [Conference Paper]

S. Hamdioui, A.J. van de Goor, M. Rodgers, March SS: A test for all static simple RAM faults (July 2002), 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France [Conference Paper]

S. Hamdioui, A.J. van de Goor, M. Rodgers, DPM Reduction On Dual Port Caches (May 2002), 7th IEEE European Test Workshop (ETW 2002), 26-29 May 2002, Corfu, Greece [Conference Paper]

S. Hamdioui, A.J. van de Goor, Efficient Tests for Realistic Faults in Dual-Port Memories (May 2002), IEEE Transactions on Computers (TC), volume 51, issue 5 [Journal Paper]

S.N. Demidenko, N. Lord, A.J. van de Goor, V. Piuri, Quasi on-line testing of embedded random access memory (April 2002), 4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Approximating Infinite Dynamic Behavior for DRAM Cell Defects (April 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Modeling techniques and tests for partial faults in memory devices (March 2002), Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France [Conference Paper]

A.J. van de Goor, M.S. Abadir, J.F. Carlin, Minimal test for coupling faults in word-oriented memories (March 2002), Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France [Conference Paper]

S. Hamdioui, A.J. van de Goor, Thorough Tesing Any Multi-Port Memory with Linear Tests (February 2002), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 21, issue 2 [Journal Paper]

S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Testing static and dynamic faults in random access memories (January 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]

A.J. van de Goor, I. Schanstra, Address and data scrambling: causes and impact on memory tests (January 2002), 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 200, Christchurch, New Zealand [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, A memory specific notation for fault modeling (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

S.N. Demidenko, A.J. van de Goor, S. Henderson, P. Knoppers, Simulation and development of short transparent tests for RAM (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers, Detecting unique faults in multi-port SRAMs (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

M. Klaus, A.J. van de Goor, Tests for resistive and capacitive defects in address decoders (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Simulation based analysis of temperature effect on the faulty behaviour of embedded DRAMs (October 2001), IEEE International Test Conference (ITC 2001), 30 October - 1 November 2001, Baltimore, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Transient faults in DRAMs: concept, analysis and impact on tests (August 2001), 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA [Conference Paper]

S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers, Realistic fault models and test procedure for multi-port SRAMs (August 2001), 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs (March 2001), Conference on Design, Automation and Test in Europe (DATE 2001), 12-16 March 2001, Munich, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, J. Braun, B. Gauch, D. Richter, W. Spirkl, Development of a DRAM simulation model for fault analysis purposes (February 2001), 13th Workshop on Testmethods and Reliability of Circuits and Systems, 18–20 February 2001, Miesbach, Germany [Conference Paper]

Z. Al-Ars, A.J. van de Goor, Impact of memory cell array bridges on the faulty behavior in embedded DRAMs (December 2000), 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan [Conference Paper]

S. Hamdioui, A.J. van de Goor, An experimental analysis of spot defects in SRAMs: realistic fault models and test (December 2000), 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan [Conference Paper]

S. Hamdioui, A.J. van de Goor, Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy (October 2000), Journal of Electronic Testing: Theory and Applications (JETTA), volume 16, issue 5 [Journal Paper]

A.J. van de Goor, A. Paalvast, Industrial Evaluation of DRAM SIMM Tests (October 2000), IEEE International Test Conference (ITC 2000), 3-5 October 2000, Atlantic City, USA , Top Ten Best Papers Awards [Conference Paper]

M.J. Geuzebroek, J. van der Linden, A.J. van de Goor, Test Point Insertion for Compact Test Sets (October 2000), IEEE International Test Conference (ITC 2000), 3-5 October 2000, Atlantic City, USA [Conference Paper]

S. Hamdioui, A.J. van de Goor, M. Rodgers, D. Eastwick, March tests for realistic faults in two-port memories (August 2000), 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, USA [Conference Paper]

A.J. van de Goor, Z. Al-Ars, Functional memory faults: a formal notation and a taxonomy (April 2000), 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada [Conference Paper]