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C. Weis

NameC. Weis
First NameChristian
E-mail
Author TypeExternal
AffiliationTU Kaisersluatern

Publications

K. Chandrasekar, S.L.M. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, K.G.W. Goossens, Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization 1399_exploiting_expendable_processmargins_in_drams_for_runtime.pdf (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Paper]
K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K.G.W. Goossens, Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach 1342_towards_variationaware_systemlevel_power_estimation_of_dr.pdf (June 2013), 50th Design Automation Conference (DAC 2013), 2-6 June 2013, Austin, USA , HiPEAC Paper Award [Conference Paper]
K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K.G.W. Goossens, System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs 1323_system_and_circuit_level_power_modeling_of_energyefficient.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
M. Jung, C. Weis, K. Chandrasekar, N. Wehn, TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems 1332_tlm_modelling_of_3d_stacked_wide_io_dram_subsystems.pdf (January 2013), 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2013), 21 January 2013, Berlin, Germany [Conference Paper]