K. Chandrasekar, High-Level Power Estimation and Optimization of DRAMs (October 2014), [Phd Thesis]

K. Chandrasekar, S.L.M. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, K.G.W. Goossens, Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Paper]

K.G.W. Goossens, A. Azevedo, K. Chandrasekar, M. Gomony, S.L.M. Goossens, M. Koedam, Y. Li, D. Mirzoyan, A.M. Molnos, A. Beyranvand Nejad, A.T. Nelson, S. Sinha, Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow (October 2013), ACM SIGBED Special Interest Group on Embedded Systems Review, volume 10, issue 3 [Journal Paper]

K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K.G.W. Goossens, Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach (June 2013), 50th Design Automation Conference (DAC 2013), 2-6 June 2013, Austin, USA , HiPEAC Paper Award [Conference Paper]

K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K.G.W. Goossens, System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]

M. Jung, C. Weis, K. Chandrasekar, N. Wehn, TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems (January 2013), 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2013), 21 January 2013, Berlin, Germany [Conference Paper]

G. Thomas, K. Chandrasekar, B. Akesson, B.H.H. Juurlink, K.G.W. Goossens, A Predictor-based Power-Saving Policy for DRAM Memories (September 2012), 15th Euromicro Conference on Digital System Design (DSD 2012), 5-8 September 2012, Izmir, Turkey [Conference Paper]

K. Chandrasekar, B. Akesson, K.G.W. Goossens, Run-Time Power-Down Strategies for RealTime SDRAM Memory Controllers (June 2012), Design Automation Conference (DAC 2012), 3-7 June 2012, San Fransisco, USA , HiPEAC Paper Award [Conference Paper]

K. Chandrasekar, B. Akesson, K.G.W. Goossens, Predictable Power-Down Policies for SDRAMs (November 2011), ICT.OPEN 2011, 14-15 November 2011 , Veldhoven, The Netherlands , Poster [Conference Paper]

K. Chandrasekar, B. Akesson, K.G.W. Goossens, Improved Power Modeling of DDR SDRAMs (September 2011), 14th Euromicro Conference On Digital System Design (DSD 2011), 31 August - 2 September 2011, Oulu, Finland [Conference Paper]

K. Chandrasekar, B. Akesson, K.G.W. Goossens, Modeling and Optimizing Power for a Real-Time SDRAM Controller (November 2010), Annual Workshop on PROGram for Research on Embedded Systems & Software (PROGRESS), November 2010, Veldhoven, The Netherlands , Poster [Conference Paper]

K. Chandrasekar, Performance Validation of Networks on Chip (November 2009), [Msc Thesis]