C Papameletis, B. Keller, V. Chickermane, S. Hamdioui, E.J. Marinissen, A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers (April 2015), IEEE Design & Test of Computers (D&ToC), volume 32, issue 4 [Journal Paper]

C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, S. Hamdioui, Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Paper]

C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Proceedings]