M. Taouil, S. Hamdioui, E.J. Marinissen, Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching (June 2015), ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 20, issue 2 [Journal Paper]

M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Post-Bond Interconnect Test and Diagnosis for 3D Memory Stacked on Logic (May 2015), IEEE Transactions on Computers (TC), issue 99 [Journal Paper]

C Papameletis, B. Keller, V. Chickermane, S. Hamdioui, E.J. Marinissen, A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers (April 2015), IEEE Design & Test of Computers (D&ToC), volume 32, issue 4 [Journal Paper]

E.J. Marinissen, B de Wachter, K Smith, J Kiesewetter, M. Taouil, S. Hamdioui, Direct Probing on Large-Array Fine-Pitch Micro-Bumps of a Wide-I/O Logic-Memory Interface. (October 2014), International Test Conference (ITC 2014), 21-23 October 2014, Seattle, USA [Conference Proceedings]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Quality versus Cost Analysis for 3D Stacked ICs (April 2014), 32nd IEEE VLSI Test Symposium (VTS 2014), 13-17 April 2014, Napa, USA [Conference Proceedings]

M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Interconnect Test for 3D Stacked Memory-on-Logic (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Proceedings]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Impact of Mid-Bond Testing in 3D Stacked ICs (October 2013), 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Using 3D-COSTAR for 2.5D Test Cost Optimization (October 2013), IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA [Conference Paper]

C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, S. Hamdioui, Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Paper]

C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Proceedings]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, 3D-COSTAR: A Cost Model For 3D Stacked ICs (November 2012), Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012), 8-9 November 2012, Anaheim, USA [Conference Proceedings]

M. Taouil, S. Hamdioui, E.J. Marinissen, On Modeling and Optimizing Cost in 3D Stacked-ICs (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]

M. Taouil, S. Hamdioui, C.I.M. Beenakker, E.J. Marinissen, Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost (December 2011), Journal of Electronic Testing: Theory and Applications (JETTA), volume 28, issue 1 [Journal Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Modeling for 3D-Stacked ICs (September 2011), Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 22-23 September 2011, Anaheim, USA [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs? (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking (December 2010), 19th IEEE Asian Test Symposium (ATS 2010), 1-4 December 2010, Shanghai, China [Conference Paper]

E.J. Marinissen, C.C. Chi, J. Verbree, M. Konijnenburg, 3D DfT Architecture for Pre-Bond and Post-Bond Testing (November 2010), IEEE International Conference on 3D System Integration (3DIC 2010), 16-18 November 2010, Munich, Germany [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking (November 2010), First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 4-5 November 2010, Austin, USA [Conference Paper]

M. Taouil, S. Hamdioui, J. Verbree, E.J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]

A.J. van den Berg, P. Ren, E.J. Marinissen, G.N. Gaydadjiev, K.G.W. Goossens, Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism (July 2010), Journal of Electronic Testing: Theory and Applications (JETTA), volume 26, issue 4 [Journal Paper]

B. Noia, S.K. Goel, K. Chakrabarty, E.J. Marinissen, J. Verbree, Test-architecture optimization for TSV-based 3D stacked ICs (May 2010), 15th IEEE European Test Symposium (ETS 2010), 25-28 May 2010, Prague, Czech Republic [Conference Paper]

J. Verbree, E.J. Marinissen, P. Roussel, D. Velenis, On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking (May 2010), 15th IEEE European Test Symposium (ETS 2010), 25-28 May 2010, Prague, Czech Republic [Conference Paper]

E.J. Marinissen, J. Verbree, M. Konijnenburg, A structured and scalable test access architecture for TSV-based 3D stacked ICs (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]

J. Verbree, E.J. Marinissen, P. Roussel, D. Velenis, Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany , Poster at DATE 2010 Friday Workshop [Conference Paper]