S. Hamdioui

NameS. Hamdioui
First NameSaid
E-mailS.Hamdioui@tudelft.nl
Author TypeStaff
AffiliationTU Delft

Publications

L. Xie, H.A. Du Nguyen, J. Yu, A. Kaichouhi, M. Taouil, S. Hamdioui, Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing (July 2017), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), 3-5 July 2017, Bochum, Germany [Conference Proceedings]
H.A. Du Nguyen, L. Xie, M. Taouil, R. Nane, S. Hamdioui, K.L.M. Bertels, On the Implementation of Computation-in-Memory Parallel Adder (May 2017), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI) [Journal Paper]
M. Barbareschi, A. Bosio, H.A. Du Nguyen, S. Hamdioui, M. Traiola, E. I. Vatajelu, Memristive devices: Technology, Design Automation and Computing Frontiers (April 2017), 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain [Conference Paper]
H.A. Du Nguyen, L. Xie, J. Yu, M. Taouil, S. Hamdioui, Interconnect Networks for Resistive Computing Architectures (April 2017), 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain [Conference Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar (April 2017), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) [Journal Paper]
L. Xie, H.A. Du Nguyen, J. Yu, M. Taouil, S. Hamdioui, On the Robustness of Memristor Based Logic Gates (April 2017), IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017, Dresden, Germany [Conference Proceedings]
I.O. Agbo, M. Taouil, D.H.P. Kraak, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier (April 2017), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 25, issue 4 [Journal Paper]
E. I. Vatajelu, P. Prinetto, M. Taouil, S. Hamdioui, Challenges and Solutions in Emerging Memory Testing (April 2017), IEEE Transactions on Emerging Topics in Computing [Journal Paper]
S. Hamdioui, S Kvatinsky, G Cauwenberghs, L. Xie, N Wald, S Joshi, H Elsayed, H. Corporaal, K.L.M. Bertels, Memristor For Computing: Myth or Reality? (March 2017), Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland [Conference Proceedings]
A. Scionti, S. Mazumdar, S. Di Carlo, S. Hamdioui, SIERRA - Simulation environment for memory redundancy algorithms (December 2016), Simulation Modelling Practice and Theory, volume 69 [Journal Paper]
G. Ch Sirakoulis, S. Hamdioui, Editorial Note on Memristor Models, Circuits and Architectures (December 2016), International Journal of Unconventional Computing (IJUC), volume 12, issue 4 [Journal Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, M Alfailakawi, Non-Volatile Look-up Table Based FPGA Implementations 1604_nonvolatile_lookup_table_based_fpga_implementations.pdf (December 2016), 11th IEEE International Design & Test Symposium (IDT 2016), 18-20 December 2016, Hammamet, Tunisia [Conference Proceedings]
D.H.P. Kraak, I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene, On Mitigating Sense Amplifier Offset Voltage Degradation 1590_on_mitigating_sense_amplifier_offset_voltage_degradation.pdf (November 2016), First IEEE International Workshop on Automotive Reliability & Test (ART Workshop 2016), 17-18 November 2016, Fort Worth, USA [Conference Paper]
P. Pouyan, S. Hamdioui, A. Rubio, RRAM Variability and Its Mitigation Schemes 1569_rram_variability_and_its_mitigation_schemes.pdf (September 2016), PATMOS & VARI 2016 (PATMOS & VARI 2016), 21-23 September 2016, Bremen, Germany , Best Paper Award [Conference Proceedings]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, CIM Architecture Communication Schemes (September 2016), The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (IMISCET 2016), 11 September 2016, Haifa, Israel [Conference Paper]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels, CIMx: Computation in-Memory Architecture Based on Resistive Devices (August 2016), 15th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2016), 23-25 August 2016, Dresden, Germany [Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, Synthesizing HDL to memristor technology: A generic framework (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China [Conference Paper]
M.A.B. Haron, J. Yu, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels, Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture 1550_parallel_matrix_multiplication_on_memristorbased_computati.pdf (July 2016), International Conference on High Performance Computing & Simulation (HPCS 2016), 18-22 July 2016, Innsbruck, Austria , Outstanding Paper Runner-up Award [Conference Paper]
J. Yu, R. Nane, M.A.B. Haron, S. Hamdioui, H. Corporaal, K.L.M. Bertels, Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures 1544_skeletonbased_design_and_simulation_flow_for_computationi.pdf (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China , Best Student Paper Award [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene, Quantification of Sense Amplifier Offset Voltage Degradation due to Zero- and Run-time Variability 1543_quantification_of_sense_amplifier_offset_voltage_degradatio.pdf (July 2016), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), 11-13 July 2016, Pittsburgh, U.S.A. , Best Paper Award [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene, Read Path Degradation Analysis in SRAM 1540_read_path_degradation_analysis_in_sram.pdf (May 2016), IEEE European Test Symposium (ETS 2016), 24-27 May 2016, Amsterdam, The Netherlands [Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Boolean Logic Gate Exploration for Memristor Crossbar (April 2016), 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2016), 12-14 april 2016, Istanbul, Turkey [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, Comparative BTI Analysis for Various Sense Amplifier Designs 1532_comparative_bti_analysis_for_various_sense_amplifier_design.pdf (April 2016), IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 20-22 April 2016, Košice, Slovakia [Conference Proceedings]
A Gebregiorgis, F Oboril, M Baradaran Tahoori, S. Hamdioui, Instruction cache aging mitigation through Instruction Set Encoding (March 2016), 17th International Symposium on Quality Electronic Design (ISQED 2016), 14-16 March 2016, Santa Clara, USA [Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, CIM Based Parallel Adder Implementations and Evaluations (January 2016), Workshop on Memristor Technology, Design, Automation and Computing (MemTDAC 2016), 20 January 2016, Prague, Czech republic [Conference Paper]
I Vourkas, D Stathis, G. Ch Sirakoulis, S. Hamdioui, Alternative Architectures towards Reliable Memristive Crossbar Memories 1509_alternative_architectures_towards_reliable_memristive_cross.pdf (January 2016), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 24, issue 1 [Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, BTI Analysis of SRAM Write Driver 1521_bti_analysis_of_sram_write_driver.pdf (December 2015), 10th IEEE International Design & Test Symposium (IDT 2015), 14-16 December 2015, Dead Sea, Jordan [Conference Proceedings]
A Gebregiorgis, M Ebrahimi, S Kiamehr, F Oboril, S. Hamdioui, M Baradaran Tahoori, Aging mitigation in memory arrays using selfcontrolled bit-flipping technique (November 2015), 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), 19-22 January 2015, Tokyo, Japan [Conference Proceedings]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels, Memristor: The Enabler of Computation-in-Memory Architecture for Big-Data (November 2015), International Conference on Memristive Systems (MEMRISYS 2015), 8 - 10 November 2015, Paphos, Cyprus [Conference Proceedings]
L Brasca, M Sonza Reorda, S. Hamdioui, SW-based transparent in-field memory testing (November 2015), 16th IEEE Latin-American Test Symposium (LATS 2015), 25-27 March 2015, Puerto Vallarta, Mexico [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene, Comparative BTI Impact for SRAM Cell and Sense Amplifier Designs 1516_comparative_bti_impact_for_sram_cell_and_sense_amplifier_de.pdf (November 2015), MEDIAN Finale - Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2015), 10-11 November 2015, Tallinn, Estonia [Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Fast Boolean Logic Mapped on Memristor Crossbar 1505_fast_boolean_logic_mapped_on_memristor_crossbar.pdf (October 2015), 33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA , Best Paper Award [Conference Paper]
H.A. Du Nguyen, L. Xie, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels, Computation-In-Memory Based Parallel Adder 1497_computationinmemory_based_parallel_adder.pdf (July 2015), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA [Conference Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Interconnect Networks for Memristor Crossbar (July 2015), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA [Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching (June 2015), ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 20, issue 2 [Journal Paper]
Y Sfikas, Y Tsiatouhas, M. Taouil, S. Hamdioui, On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect (May 2015), 20th IEEE European Test Symposium (ETS 2015), 25-29 May 2015, Cluj-Napoca, Romania [Conference Proceedings]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Post-Bond Interconnect Test and Diagnosis for 3D Memory Stacked on Logic (May 2015), IEEE Transactions on Computers (TC), issue 99 [Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, Integral Impact of BTI and Voltage Temperature Variation on SRAM Sense Amplifier 1483_integral_impact_of_bti_and_voltage_temperature_variation_on.pdf (April 2015), IEEE VLSI Test Symposium (VTS 2015), 27-29 April 2015, Napa, USA [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, S. Cosemans, P Weckx, P. Raghavan, F. Catthoor, Comparative Analysis of R-D and Atomistic Trap-Based BTI models on SRAM Sense Amplifier 1482_comparative_analysis_of_rd_and_atomistic_trapbased_bti_mo.pdf (April 2015), Design and Technology of Integrated Systems in the Nanoscale Era (DTIS 2015), 21-23 April 2015, Naples, Italy , Best Paper Award [Conference Proceedings]
A.M.M.O. Cortez, S. Hamdioui, A. Kaichouhi, V. van der Leest, R. Maes, G.J. Schrijen, Intelligent Voltage Ramp-up Time Adaptation for Temperature Noise Reduction on Memory-based PUF Systems 1474_intelligent_voltage_rampup_time_adaptation_for_temperature.pdf (April 2015), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 34, issue 7 , DOI: 10.1109/TCAD.2015.2422844 [Journal Paper]
A.M.M.O. Cortez, S. Hamdioui, G. Di Natale, M.-L. Flottes, B. Rouzeyre, Hierarchical Secure DfT (March 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2015), 13 March 2015, Grenoble, France [Conference Paper]
A.M.M.O. Cortez, S. Hamdioui, R. Ishihara, Design Dependent SRAM PUF Robustness Analysis 1472_design_dependent_sram_puf_robustness_analysis.pdf (March 2015), 16th IEEE Latin-American Test Symposium (LATS 2015), 25-27 March 2015, Puerto Vallarta, Mexico , DOI: 10.1109/LATW.2015.7102498 [Conference Paper]
S. Hamdioui, L. Xie, H.A. Du Nguyen, M. Taouil, K.L.M. Bertels, Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications 1476_memristor_based_computationinmemory_architecture_for_data.pdf (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, BTI Analysis for High Performance and Low power SRAM Sense Amplifier 1461_bti_analysis_for_high_performance_and_low_power_sram_sense.pdf (March 2015), 4th Workshop On Manufacturable and Dependable Multicore Architectures (MEDIAN 2015), 13 March 2015, Grenoble, France [Conference Paper]
S. Hamdioui, M. Taouil, N.Z.B. Haron, Testing Open Defects in Memristor-Based Memories 1409_testing_open_defects_in_memristorbased_memories.pdf (January 2015), IEEE Transactions on Computers (TC), volume 64, issue 1 [Journal Paper]
E.J. Marinissen, B de Wachter, K Smith, J Kiesewetter, M. Taouil, S. Hamdioui, Direct Probing on Large-Array Fine-Pitch Micro-Bumps of a Wide-I/O Logic-Memory Interface. (October 2014), International Test Conference (ITC 2014), 21-23 October 2014, Seattle, USA [Conference Proceedings]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale, Testing Methods for PUF-Based Secure Key Storage Circuits 1438_testing_methods_for_pufbased_secure_key_storage_circuits.pdf (October 2014), Journal of Electronic Testing: Theory and Applications (JETTA), volume 30, issue 5 , Digital Object Identifier (DOI): 10.1007/s10836-014-5471-7 [Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Impact of BTI on SRAM Sense Amplifier in the Presence of Temperature and Process Variation 1453_impact_of_bti_on_sram_sense_amplifier_in_the_presence_of_te.pdf (September 2014), Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands [Conference Proceedings]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale, Secure Test Method for Fuzzy Extractor (September 2014), Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands [Conference Paper]
P. D Joshi, S. Hamdioui, Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures (July 2014), IEEE 15th International Conference on High Performance Switching and Routing (HPSR 2014), 1-4 July 2014, Vancouver, Canada [Conference Proceedings]
Y Sfikas, Y Tsiatouhas, S. Hamdioui, Layout-Based Refined NPSF Model for DRAM Characterization and Testing (June 2014), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 22 [Journal Paper]
S. Hamdioui, H Aziza, G. Ch Sirakoulis, Memristor based memories: Technology, design and test (May 2014), IEEE 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2014), 6-8 May 2014, Santorini, Greece [Conference Proceedings]
S. Hamdioui, 3D/ 2.5D stacked IC cost modeling and test flow selection (May 2014), IEEE 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2014), 6-8 May 2014, Santorini, Greece [Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Quality versus Cost Analysis for 3D Stacked ICs (April 2014), 32nd IEEE VLSI Test Symposium (VTS 2014), 13-17 April 2014, Napa, USA [Conference Proceedings]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale, Testing PUF-based Secure Key Storage Circuits 1395_testing_pufbased_secure_key_storage_circuits.pdf (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Paper]
M.S. Khan, I.O. Agbo, S. Hamdioui, H. Kukner, B Kaczer, P. Raghavan, F. Catthoor, Bias Temperature Instability analysis of FinFET based SRAM cells 1452_bias_temperature_instability_analysis_of_finfet_based_sram.pdf (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Proceedings]
H. Kukner, M.S. Khan, S. Hamdioui, P. Raghavan, F. Catthoor, Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates 1372_comparison_of_reactiondiffusion_and_atomistic_trapbased_b.pdf (March 2014), IEEE Transactions on Reliability (TR), volume 14, issue 1 [Journal Paper]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Interconnect Test for 3D Stacked Memory-on-Logic (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Proceedings]
S. Hamdioui, G. Di Natale, G van Battum, J Danger, F Smailbegovic, M Tehranipoor, Hacking and Protecting IC Hardware (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Paper]
I.O. Agbo, M.S. Khan, S. Hamdioui, BTI Impact on SRAM Sense Amplifier 1418_bti_impact_on_sram_sense_amplifier.pdf (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
L.M. Ciganda, P. Bernardi, M. Sonza Reorda, S. Hamdioui, An efficient method for the test of embedded memory cores during the operational phase (November 2013), 22nd Asian Test Symposium (ATS 2013), 18-21 November 2013, Yilan, Taiwan [Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Impact of Mid-Bond Testing in 3D Stacked ICs 1389_impact_of_midbond_testing_in_3d_stacked_ics.pdf (October 2013), 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Using 3D-COSTAR for 2.5D Test Cost Optimization 1388_using_3dcostar_for_25d_test_cost_optimization.pdf (October 2013), IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA [Conference Paper]
A.M.M.O. Cortez, V. van der Leest, R. Maes, G.J. Schrijen, S. Hamdioui, Adapting Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs 1345_adapting_voltage_rampup_time_for_temperature_noise_reducti.pdf (June 2013), IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2013), 2-3 June 2013, Austin, USA [Conference Paper]
C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, S. Hamdioui, Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers 1419_automated_dft_insertion_and_test_generation_for_3dsics_wit.pdf (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Paper]
M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Bias temperature instability analysis in SRAM decoder (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Paper]
M. Lefter, G.R. Voicu, M. Taouil, M. Enachescu, S. Hamdioui, S.D. Cotofana, Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? 1328_is_tsvbased_3d_integration_suitable_for_interdie_memory_r.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
S. Hamdioui, D. Gizopoulos, G. Guido, M. Nicolaidis, A. Grasset, P. Bonnot, Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes 1411_reliability_challenges_of_realtime_systems_in_forthcoming.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Proceedings]
A.M.M.O. Cortez, S. Hamdioui, V. van der Leest, R. Maes, G.J. Schrijen, Noise Reduction on Memory-based PUFs 1396_noise_reduction_on_memorybased_pufs.pdf (March 2013), 1st Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2013), 30-31 May 2013, Avignon, France [Conference Paper]
M.S. Khan, S. Hamdioui, Variability and Reliability Analyses in SRAM Decoder 1340_variability_and_reliability_analyses_in_sram_decoder.pdf (January 2013), 4th Workshop on Design for Reliability (DFR 2012), 23-25 January 2012, Paris, France [Conference Paper]
S. Hamdioui, Testing Embedded Memories: A Survey 1422_testing_embedded_memories_a_survey.pdf (January 2013), Mathematical and Engineering Methods in Computer Science, issue Springer Berlin Heidelberg [Journal Paper]
M.S. Khan, S. Hamdioui, M. Taouil, H. Kukner, P. Raghavan, F. Catthoor, Impact of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder Reliablity 1338_impact_of_partial_resistive_defects_and_bias_temperature_in.pdf (December 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Proceedings]
M. Taouil, M. Lefter, S. Hamdioui, Exploring Test Opportunities for Memory and Interconnects in 3D ICs 1337_exploring_test_opportunities_for_memory_and__interconnects.pdf (December 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, 3D-COSTAR: A Cost Model For 3D Stacked ICs 1339_3dcostar_a_cost_model_for_3d_stacked_ics.pdf (November 2012), Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012), 8-9 November 2012, Anaheim, USA [Conference Proceedings]
M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis 1299_incorporating_parameter_variations_in_bti_impact_on_nanosc.pdf (October 2012), IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 3-5 October 2012, Austin, USA [Conference Paper]
A.M.M.O. Cortez, A. Dargar, G.J. Schrijen, S. Hamdioui, Modeling SRAM Start-Up Behavior for Physical Unclonable Functions 1298_modeling_sram_startup_behavior_for_physical_unclonable_fun.pdf (October 2012), IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 3-5 October 2012, Austin, USA , Best Student Paper Award [Conference Paper]
A.M.M.O. Cortez, V. van der Leest, G.J. Schrijen, S. Hamdioui, Investigation of Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs (October 2012), ICT.OPEN 2012 (ICT.OPEN 2012), 22-23 October 2012, Rotterdam, The Netherlands [Conference Paper]
M. Taouil, S. Hamdioui, Yield Improvement for 3D Wafer-to-Wafer Stacked Memories 1341_yield_improvement_for_3d_wafertowafer_stacked_memories.pdf (August 2012), Journal of Electronic Testing: Theory and Applications (JETTA), volume 28 , issue 4 [Journal Paper]
M.S. Khan, S. Hamdioui, Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates 1297_analyzing_combined_impacts_of_parameter_variations_and_bti.pdf (June 2012), 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012), 1 June 2012, Annecy, France [Conference Paper]
M. Taouil, S. Hamdioui, On Optimizing Test Cost for Wafer-to-Wafer 3D Stacked ICs 1296_on_optimizing_test_cost_for_wafertowafer_3d_stacked_ics.pdf (May 2012), 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 16-18 May 2012, Tunis, Tunisia [Conference Paper]
M.S. Khan, S. Hamdioui, H. Kukner, F. Catthoor, P. Raghavan, BTI Impacts on Logical Gates in Nano-scale CMOS Technology 134_bti_impacts_on_logical_gates_in_nanoscale_cmos_technology.pdf (April 2012), 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), 18-20 April 2012, Tallinn, Estonia [Conference Paper]
N.Z.B. Haron, S. Hamdioui, DfT Schemes for Resistive Open Defects in RRAMs 131_dft_schemes_for_resistive_open_defects_in_rrams.pdf (March 2012), Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), 12-16 March 2012, Dresden, Germany [Conference Paper]
M.S. Khan, S. Hamdioui, F. Catthoor, Comparative BTI Analysis in Nano-scale Circuits Lifetime 122_comparative_bti_analysis_in_nanoscale_circuits_lifetime.pdf (January 2012), 4th Workshop on Design for Reliability (DFR 2012), 23-25 January 2012, Paris, France [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, On Modeling and Optimizing Cost in 3D Stacked-ICs (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]
M.S. Khan, S. Hamdioui, ReverseAge: an Online NBTI Combating Technique Using Time Borrowing 93_reverseage_an_online_nbti_combating_technique_using_time_bor.pdf (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]
M. Taouil, S. Hamdioui, C.I.M. Beenakker, E.J. Marinissen, Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost 92_test_impact_on_the_overall_dietowafer_3d_stacked_ic_cost.pdf (December 2011), Journal of Electronic Testing: Theory and Applications (JETTA), volume 28, issue 1 [Journal Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Testing for Parasitic Memory Effect in SRAMs 99_testing_for_parasitic_memory_effect_in_srams.pdf (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
N.Z.B. Haron, S. Hamdioui, On Defect Oriented Testing for Hybrid CMOS/memristor Memory 98_on_defect_oriented_testing_for_hybrid_cmosmemristor_memory.pdf (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
S. Hamdioui, M. Taouil, Yield Improvement and Test Cost Optimization for 3D Stacked ICs (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
M.S. Khan, S. Hamdioui, N.Z.B. Haron, F. Catthoor, NBTI Monitoring and Design for Reliability in Nanoscale Circuits 106_nbti_monitoring_and_design_for_reliability_in_nanoscale_circ.pdf (October 2011), IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011), 3-5 October 2011, Vancouver, Canada [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Modeling for 3D-Stacked ICs (September 2011), Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 22-23 September 2011, Anaheim, USA [Conference Paper]
M.S. Khan, S. Hamdioui, Modeling and Mitigating NBTI in Nanoscale Circuits 33_modeling_and_mitigating_nbti_in_nanoscale_circuits.pdf (July 2011), 17th IEEE International On-Line Testing Symposium (IOLTS), 13-15 July 2011, Athens, Greece [Conference Paper]
M. Taouil, S. Hamdioui, Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs 61_memory_test_optimization_for_parasitic_bit_line_coupling_in_s.pdf (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]
M. Taouil, S. Hamdioui, Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs? (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece [Conference Paper]
A.J. van de Goor, H. Kukner, S. Hamdioui, Optimizing Memory BIST Address Generator Implementations 72_optimizing_memory_bist_address_generator_implementations.pdf (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece , Best Paper Award [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell, Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs 71_influence_of_parasitic_memory_effect_on_singlecell_faults_in.pdf (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories 77_costefficient_faulttolerant_decoder_for_hybrid_nanoelectron.pdf (March 2011), Design, Automation and Test in Europe (DATE 2011), 14-18 March 2011, Grenoble, France [Conference Paper]
A.J. van de Goor, S. Hamdioui, H. Kukner, Generic, Orthogonal and Low-Cost March Element-based Memory BIST 1336_generic_orthogonal_and_lowcost_march_elementbased_memory.pdf (January 2011), IEEE International Test Conference (IEEE ITC), 20-22 Sept, Anaheim, CA, USA [Conference Proceedings]
N.Z.B. Haron, S. Hamdioui, On Correcting Cluster Errors in Nanoelectronic Memories 117_on_correcting_cluster_errors_in_nanoelectronic_memories.pdf (January 2011), 3rd HiPEAC Workshop on Design for Reliability (DFR 2011), 23 January 2011, Heraklion, Greece [Conference Paper]
M.S. Khan, S. Hamdioui, NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation 115_nbtiaware_nanoscaled_circuit_delay_assessment_and_mitigatio.pdf (January 2011), 3rd HiPEAC Workshop on Design for Reliability (DFR 2011), 23 January 2011, Heraklion, Greece [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories 113_redundant_residue_number_system_code_for_faulttolerant_hybr.pdf (January 2011), ACM Journal on Emerging Technologies in Computing Systems (JETC), volume 7, issue 1 , article 4 [Journal Paper]
A.J. van de Goor, S. Hamdioui, MBIST Architecture Framework based on Orthogonal Constructs (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Z. Ahyadi, ECC Design for Fault-Tolerant Crossbar Memories: A Case Study 235_ecc_design_for_faulttolerant_crossbar_memories_a_case_stud.pdf (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking 227_test_cost_analysis_for_3d_dietowafer_stacking.pdf (December 2010), 19th IEEE Asian Test Symposium (ATS 2010), 1-4 December 2010, Shanghai, China [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking 252_impact_of_test_flows_on_the_cost_in_3d_dietowafer_stacking.pdf (November 2010), First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 4-5 November 2010, Austin, USA [Conference Paper]
M. Taouil, S. Hamdioui, J. Verbree, E.J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs 249_on_maximizing_the_compound_yield_for_3d_wafertowafer_stack.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Detecting Memory Faults in the Presence of Bit Line Coupling in SRAM Devices 248_detecting_memory_faults_in_the_presence_of_bit_line_coupling.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
N.Z.B. Haron, S. Hamdioui, High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories 261_highperformance_clusterfault_tolerance_scheme_for_hybrid_n.pdf (October 2010), 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2010), 6-8 October 2010, Kyoto, Japan [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Mitigating Defective CMOS to Non-CMOS Vias in CMOS/Molecular Memories 156_mitigating_defective_cmos_to_noncmos_vias_in_cmosmolecular.pdf (August 2010), 10th IEEE International Conference on Nanotechnology (NANO 2010), August 2010, Seoul, Korea , Certificate of Merit [Conference Paper]
M.S. Khan, S. Hamdioui, Temperature Dependence of NBTI Induced Delay 160_temperature_dependence_of_nbti_induced_delay.pdf (July 2010), 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July 2010, Corfu, Greece [Conference Paper]
A.J. van de Goor, C. Jung, S. Hamdioui, G.N. Gaydadjiev, Low-cost, Customized and Flexible SRAM MBIST Engine (April 2010), 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs 202_bit_line_coupling_memory_tests_for_singlecell_fails_in_sram.pdf (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]
A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev, Using a CISC microcontroller to test embedded memories (April 2010), 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria [Conference Paper]
A.J. van de Goor, G.N. Gaydadjiev, S. Hamdioui, Memory Testing with a RISC Microcontroller 213_memory_testing_with_a_risc_microcontroller.pdf (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany [Conference Paper]
M.S. Khan, S. Hamdioui, NBTI Modeling in the Framework of Temperature Variation 212_nbti_modeling_in_the_framework_of_temperature_variation.pdf (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany [Conference Paper]
M.S. Khan, S. Hamdioui, Trends and challenges of SRAM reliability in the nano-scale era 209_trends_and_challenges_of_sram_reliability_in_the_nanoscale.pdf (March 2010), 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS 2010), 23-25 March 2010, Hammamet, Tunisia [Conference Paper]
M.S. Khan, S. Hamdioui, Temperature Impact on NBTI Modeling in the Framework of Technology Scaling 273_temperature_impact_on_nbti_modeling_in_the_framework_of_tech.pdf (January 2010), 2nd HiPEAC Workshop on Design for Reliability (DFR 2010), 24 January 2010, Pisa, Italy [Conference Paper]
Z. Al-Ars, S. Hamdioui, Non-Algorithmic Stress Optimization Using Simulation for DRAMs 394_nonalgorithmic_stress_optimization_using_simulation_for_dra.pdf (November 2009), 4th International Design and Test Workshop (IDT 2009), 15-17 November 2009, Riyadh, Saudi Arabia [Conference Paper]
Z. Al-Ars, S. Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories 393_fault_diagnosis_using_test_primitives_in_random_access_memor.pdf (November 2009), 18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan [Conference Paper]
A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev, New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults 392_new_algorithms_for_address_decoder_delay_faults_and_bit_line.pdf (November 2009), 18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories 401_using_rrns_codes_for_cluster_faults_tolerance_in_hybrid_memo.pdf (October 2009), 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2009), 7-9 October 2009, Chicago, USA [Conference Paper]
D. Borodin, B.H.H. Juurlink, S. Hamdioui, S. Vassiliadis, Instruction-Level Fault Tolerance Configurability 400_instructionlevel_fault_tolerance_configurability.pdf (October 2009), Journal of Signal Processing Systems (JSPS), volume 57, issue 1 [Journal Paper]
N.Z.B. Haron, S. Hamdioui, Residue-Based Code for Reliable Hybrid Memories 309_residuebased_code_for_reliable_hybrid_memories.pdf (July 2009), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009), 30-31 July 2009, San Fransisco, USA [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Fault Tolerance Architecture for Reliable Hybrid CMOS/Nanodevice Memories 345_fault_tolerance_architecture_for_reliable_hybrid_cmosnanode.pdf (May 2009), 14th IEEE European Test Symposium (ETS 2009), 25-29 May 2009, Sevilla, Spain [Conference Paper]
S. Hamdioui, Z. Al-Ars, Scan More with Memory Scan Test 355_scan_more_with_memory_scan_test.pdf (April 2009), 4th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2009), 6-9 April 2009, Cairo, Egypt [Conference Paper]
N.Z.B. Haron, S. Hamdioui, S.D. Cotofana, Emerging Non-CMOS Nanoelectronic Devices - What Are They? 412_emerging_noncmos_nanoelectronic_devices__what_are_they.pdf (January 2009), 4th IEEE International Conference of Nano/Micro Engineered & Molecular Systems (IEEE-NEMS 2009), 5-8 January 2009, Shenzhen, China [Conference Paper]
Z. Al-Ars, S. Hamdioui, Evaluation of SRAM Faulty Behavior Under Bit Line Coupling 516_evaluation_of_sram_faulty_behavior_under_bit_line_coupling.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
S. Hamdioui, Z. Al-Ars, Efficient Tests and DFT for RAM Address Decoder Delay Faults 515_efficient_tests_and_dft_for_ram_address_decoder_delay_faults.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Why is CMOS scaling coming to an END? 510_why_is_cmos_scaling_coming_to_an_end.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia [Conference Paper]
K. Yamasaki, S. Hamdioui, Z. Al-Ars, A.J. van Genderen, G.N. Gaydadjiev, High Quality Simulation Tool for Memory Redundancy Algorithms 535_high_quality_simulation_tool_for_memory_redundancy_algorithm.pdf (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]
M.S. Khan, S. Hamdioui, N.Z.B. Haron, CMOS scaling impacts on Reliability, What do we understand? 529_cmos_scaling_impacts_on_reliability_what_do_we_understand.pdf (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]
N.Z.B. Haron, S. Hamdioui, Emerging Crossbar-based Hybrid Nanoarchitectures for Future Computing Systems 527_emerging_crossbarbased_hybrid_nanoarchitectures_for_future.pdf (November 2008), IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia [Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, BIST Enhancement for Detecting Bit/Byte Write Enable Faults in SOC SRAMs 526_bist_enhancement_for_detecting_bitbyte_write_enable_faults.pdf (November 2008), IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller, Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs 545_defect_oriented_testing_of_the_strap_problem_under_process_v.pdf (October 2008), IEEE International Test Conference (ITC 2008), 26-31 October 2008, Santa Clara, USA [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, S. Vassiliadis, Test Set Development for Cache Memory in Modern Microprocessors 471_test_set_development_for_cache_memory_in_modern_microprocess.pdf (June 2008), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 16, issue 6 [Journal Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Precise Identification of Memory Faults Using Electrical Simulation 647_precise_identication_of_memory_faults_using_electrical_si.pdf (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor, An Investigation on Capacitive Coupling in RAM Address Decoders 641_an_investigation_on_capacitive_coupling_in_ram_address_decod.pdf (December 2007), 2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt [Conference Paper]
S. Hamdioui, A. Orailoglu, Proceedings of IEEE DTIS07 571_proceedings_of_ieee_dtis07.pdf (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Proceedings]
Z. Al-Ars, S. Hamdioui, Automatic Analysis of Memory Faulty Behavior in Defective Memories 686_automatic_analysis_of_memory_faulty_behavior_in_defective_me.pdf (September 2007), International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Optimizing Test Length for Soft Faults in DRAM Devices 621_optimizing_test_length_for_soft_faults_in_dram_devices.pdf (May 2007), 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero, PPM Reduction on Embedded Memories in System on Chip 615_ppm_reduction_on_embedded_memories_in_system_on_chip.pdf (May 2007), 12th IEEE European Test Symposium (ETS 2007), 20-24 May 2007, Freiburg, Germany [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices 628_manifestation_of_precharge_faults_in_high_speed_dram_devices.pdf (April 2007), 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2007), 11-13 April 2007, Krakow, Poland [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs 771_influence_of_bit_line_coupling_and_twisting_on_the_faulty_be.pdf (December 2006), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12 [Journal Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder 768_opens_and_delay_faults_in_cmos_ram_address_decoder.pdf (December 2006), IEEE Transactions on Computers (TC), volume 55, issue 12 [Journal Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Comparison of Static and Dynamic Faults in 65nm Memory Technology 790_comparison_of_static_and_dynamic_faults_in_65nm_memory_techn.pdf (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Using Linear Tests for Transient Faults in DRAMs 789_using_linear_tests_for_transient_faults_in_drams.pdf (November 2006), 1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev, J. Vollrath, DRAM-Specific Space of Memory Tests 798_dramspecific_space_of_memory_tests.pdf (October 2006), IEEE International Test Conference (ITC 2006), 22-27 October 2006, Santa Clara, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, L. Mhamdi, G.N. Gaydadjiev, Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies 708_trends_in_tests_and_failure_mechanisms_in_deep_submicron_te.pdf (September 2006), International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006), 5-7 September 2006, Tunis, Tunesia [Conference Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, J. Vollrath, Bitline-Coupled Precharge Faults and Their Detection in Memory Devices 748_bitlinecoupled_precharge_faults_and_their_detection_in_memo.pdf (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes, Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies 747_investigation_of_singlecell_dynamic_faults_in_deepsubmicro.pdf (May 2006), 11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Space of DRAM Fault Models and Corresponding Testing 761_space_of_dram_fault_models_and_corresponding_testing.pdf (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany [Conference Paper]
S. Hamdioui, A.J. van de Goor, J.D. Reyes, M. Rodgers, Memory Test Experiment: Industrial Results and Data 807_memory_test_experiment_industrial_results_and_data.pdf (January 2006), IEE Proceedings - Computers and Digital Techniques, volume 153, issue 1 [Journal Paper]
Z. Al-Ars, S. Hamdioui, J. Vollrath, Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach 862_investigations_of_faulty_dram_behavior_using_electrical_simu.pdf (December 2005), 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R. Wadsworth, Impact of Stresses on the Fault Coverage of Memory Tests 819_impact_of_stresses_on_the_fault_coverage_of_memory_tests.pdf (August 2005), IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan [Conference Paper]
S. Hamdioui, J.D. Reyes, New Data-Background Sequences and Their Industrial Evaluation for Word-Oriented Random-Access Memories 841_new_databackground_sequences_and_their_industrial_evaluatio.pdf (June 2005), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 24, issue 6 [Journal Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor, Framework for Fault Analysis and Test Generation in DRAMs 857_framework_for_fault_analysis_and_test_generation_in_drams.pdf (March 2005), Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany [Conference Paper]
S. Hamdioui, J.D. Reyes, Z. Al-Ars, Evaluation of Intra-Word Faults in Word-Oriented RAMs 966_evaluation_of_intraword_faults_in_wordoriented_rams.pdf (November 2004), 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan [Conference Paper]
A.J. van de Goor, S. Hamdioui, R. Wadsworth, Detecting Faults in Peripheral Circuits and an Evaluation of SRAM Tests 992_detecting_faults_in_peripheral_circuits_and_an_evaluation_of.pdf (October 2004), International Test Conference (ITC 2004), 26-28 October 2004, Charlotte, USA [Conference Paper]
S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor, The State-of-the-art and Future Trends in Testing Embedded Memories 913_the_stateoftheart_and_future_trends_in_testing_embedded_m.pdf (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants 912_the_effectiveness_of_scan_test_and_its_new_variants.pdf (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]
S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor, Memory Fault Modeling Trends: A Case Study 925_memory_fault_modeling_trends_a_case_study.pdf (June 2004), Journal of Electronic Testing: Theory and Applications (JETTA), volume 20, issue 3 [Journal Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens 936_tests_for_address_decoder_delay_faults_in_rams_due_to_inter.pdf (May 2004), 9th IEEE European Test Symposium (ETS 2004), 23-26 May 2004, Corsica, France [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results 931_linked_faults_in_random_access_memories_concept_fault_mode.pdf (May 2004), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 23, issue 5 [Journal Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs 944_effects_of_bit_line_coupling_on_the_faulty_behavior_of_drams.pdf (April 2004), 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa, USA [Conference Paper]
S. Hamdioui, Testing Static Random Access Memories (March 2004), Published by Kluwer Academic Publishers [Book]
S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor, A Fault Primitive Based Analysis of Dynamic Memory Faults 1067_a_fault_primitive_based_analysis_of_dynamic_memory_faults.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, March SL: A Test For All Static Linked Memory Faults 1065_march_sl_a_test_for_all_static_linked_memory_faults.pdf (November 2003), 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China [Conference Paper]
S. Hamdioui, G.N. Gaydadjiev, Future Challenges in Memory Testing 1064_future_challenges_in_memory_testing.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs 1021_a_fault_primitive_based_analysis_of_linked_faults_in_rams.pdf (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]
S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor, Importance of Dynamic Faults for New SRAM Technologies 1035_importance_of_dynamic_faults_for_new_sram_technologies.pdf (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, Detecting intra-word faults in word-oriented memories 1040_detecting_intraword_faults_in_wordoriented_memories.pdf (April 2003), 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, USA [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests 1039_dynamic_faults_in_randomaccessmemories_concept_fault_mo.pdf (April 2003), Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2 [Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, March SS: A test for all static simple RAM faults 1107_march_ss_a_test_for_all_static_simple_ram_faults.pdf (July 2002), 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France [Conference Paper]
S. Hamdioui, A.J. van de Goor, Efficient Tests for Realistic Faults in Dual-Port Memories (May 2002), IEEE Transactions on Computers (TC), volume 51, issue 5 [Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, DPM Reduction On Dual Port Caches 1116_dpm_reduction_on_dual_port_caches.pdf (May 2002), 7th IEEE European Test Workshop (ETW 2002), 26-29 May 2002, Corfu, Greece [Conference Paper]
S. Hamdioui, A.J. van de Goor, Thorough Tesing Any Multi-Port Memory with Linear Tests (February 2002), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 21, issue 2 [Journal Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Testing static and dynamic faults in random access memories 1167_testing_static_and_dynamic_faults_in_random_access_memories.pdf (January 2002), 20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA [Conference Paper]
S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers, Detecting unique faults in multi-port SRAMs 1217_detecting_unique_faults_in_multiport_srams.pdf (November 2001), 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan [Conference Paper]
S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers, Realistic fault models and test procedure for multi-port SRAMs 1179_realistic_fault_models_and_test_procedure_for_multiport_sr.pdf (August 2001), 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA [Conference Paper]
S. Hamdioui, Testing Multi-Port Memories: Theory and Practice 1235_testing_multiport_memories_theory_and_practice.pdf (April 2001), , Outstanding Dissertation Award [Phd Thesis]
S. Hamdioui, A.J. van de Goor, An experimental analysis of spot defects in SRAMs: realistic fault models and test 1275_an_experimental_analysis_of_spot_defects_in_srams_realisti.pdf (December 2000), 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan [Conference Paper]
S. Hamdioui, A.J. van de Goor, Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy 1286_testing_address_decoder_faults_in_twoport_memories_fault.pdf (October 2000), Journal of Electronic Testing: Theory and Applications (JETTA), volume 16, issue 5 [Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, D. Eastwick, March tests for realistic faults in two-port memories 1249_march_tests_for_realistic_faults_in_twoport_memories.pdf (August 2000), 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, USA [Conference Paper]