S. Hamdioui
Name | S. Hamdioui |
---|---|
First Name | Said |
S.Hamdioui@tudelft.nl | |
Author Type | Staff |
Affiliation | TU Delft |
Publications
G. Cardoso Medeiros, L. M. Bolzani Poehls, M. Taouil, F. Luis Vargas, S. Hamdioui,
A Defect-Oriented Test Approach Using On-Chip Current Sensors for Resistive Defects in FinFET SRAMs
(September 2018),
Microelectronics Reliability, volume 88-90
[Journal Paper]
D.H.P. Kraak, M. Taouil, S. Hamdioui, M. Wasif, F. Catthoor, A. Chatterjee, A. Singh, H.J. Wunderlich, N. Karimi,
Device Aging: A Reliability and Security Concern
(July 2018),
23rd IEEE European Test Symposium (ETS 2018), 28 May - 1 June 2018, Bremen, Germany
[Conference Paper]
I.O. Agbo, M. Taouil, D.H.P. Kraak, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene,
Impact and Mitigation of SRAM Read Path Aging
(June 2018),
Microelectronics Reliability, volume 87
[Journal Paper]
M.C.R. Fieback, M. Taouil, S. Hamdioui, M. Rovatti,
Ionizing radiation modeling in DRAM transistors
(March 2018),
IEEE 19th Latin-American Test Symposium (LATS 2018), 12-16 March 2018, Sao Paulo, Brazil
, Best paper award!
[Conference Paper]
J. Yu, H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui,
Memristive Devices for Computation-In-Memory
(March 2018),
Design, Automation and Test in Europe (DATE 2018), 19-23 March 2018, Dresden, Germany
[Conference Paper]
D.H.P. Kraak, I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor,
Degradation analysis of high performance 14nm FinFET SRAM
(March 2018),
Design, Automation and Test in Europe (DATE 2018), 19-23 March 2018, Dresden, Germany
[Conference Paper]
E. I. Vatajelu, P. Pouyan, S. Hamdioui,
State of the Art and Challenges for Test and Reliability of Emerging Non-volatile Resistive Memories
(November 2017),
International Journal of Circuit Theory and Applications
[Journal Paper]
S. Hamdioui, K.L.M. Bertels, M. Taouil,
Computing device for “big data” applications using memristors
(November 2017),
filed in USA
[Patent]
S. Hamdioui, P. Pouyan, H Li, Y. Wang, A Raychowdhur, I Yoon,
Test and Reliability of Emerging Non-Volatile Memories
(November 2017),
26th IEEE Asian Test Symposium (ATS 2017), 27-30 November 2017, Taipei, Taiwan
[Conference Proceedings]
H.A. Du Nguyen, J. Yu, L. Xie, M. Taouil, S. Hamdioui, D. Fey,
Memristive devices for computing: Beyond CMOS and beyond von Neumann
(October 2017),
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017), 23-25 October 2017, Abu Dhabi, United Arab Emirates
[Conference Paper]
D.H.P. Kraak, M. Taouil, I.O. Agbo, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor,
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads
(October 2017),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI)
[Journal Paper]
E. I. Vatajelu, P. Pouyan, S. Hamdioui,
State of the art and challenges for test and reliability of emerging nonvolatile resistive memories
(October 2017),
International Journal of Circuit Theory and Applications
[Journal Paper]
J. Yu, R. Nane, I. Ashraf, M. Taouil, S. Hamdioui, H. Corporaal, K.L.M. Bertels,
Skeleton-based Synthesis Flow for Computation-In-Memory Architectures
(October 2017),
IEEE Transactions on Emerging Topics in Computing, volume PP, issue 99
, Pre-publish
[Journal Paper]
L. Xie, H.A. Du Nguyen, J. Yu, A. Kaichouhi, M. Taouil, S. Hamdioui,
Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing
(July 2017),
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), 3-5 July 2017, Bochum, Germany
[Conference Proceedings]
H.A. Du Nguyen, L. Xie, M. Taouil, R. Nane, S. Hamdioui, K.L.M. Bertels,
On the Implementation of Computation-in-Memory Parallel Adder
(May 2017),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI)
[Journal Paper]
C Sgouropoulou, I Voyiatzis, A Koutoumanos, S. Hamdioui, P. Pouyan, M Comte, P Prinetto, G Farulla, C Delgado Kloos, R Crespo Garcia,
Standards-based tools and services for building lifelong learning pathways
(May 2017),
IEEE Global Engineering Education Conference (EDUCON 2017), 25-28 April 2017, Athens, Greece
[Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels,
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar
(April 2017),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
[Journal Paper]
L. Xie, H.A. Du Nguyen, J. Yu, M. Taouil, S. Hamdioui,
On the Robustness of Memristor Based Logic Gates
(April 2017),
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017, Dresden, Germany
[Conference Proceedings]
I.O. Agbo, M. Taouil, D.H.P. Kraak, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor,
Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier
(April 2017),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 25, issue 4
[Journal Paper]
M. Barbareschi, A. Bosio, H.A. Du Nguyen, S. Hamdioui, M. Traiola, E. I. Vatajelu,
Memristive devices: Technology, Design Automation and Computing Frontiers
(April 2017),
12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain
[Conference Paper]
H.A. Du Nguyen, L. Xie, J. Yu, M. Taouil, S. Hamdioui,
Interconnect Networks for Resistive Computing Architectures
(April 2017),
12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain
[Conference Paper]
E. I. Vatajelu, P. Prinetto, M. Taouil, S. Hamdioui,
Challenges and Solutions in Emerging Memory Testing
(April 2017),
IEEE Transactions on Emerging Topics in Computing
[Journal Paper]
S. Hamdioui, S. Kvatinsky, G Cauwenberghs, L. Xie, N. Wald , S. Joshi, H. M. Elsayed, H. Corporaal, K.L.M. Bertels,
Memristor for computing: Myth or reality?
(March 2017),
Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland
[Conference Proceedings]
D.H.P. Kraak, I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene,
Mitigation of sense amplifier degradation using input switching
(March 2017),
Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland
[Conference Paper]
S. Hamdioui, S Kvatinsky, G Cauwenberghs, L. Xie, N Wald, S Joshi, H Elsayed, H. Corporaal, K.L.M. Bertels,
Memristor For Computing: Myth or Reality?
(March 2017),
Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland
[Conference Proceedings]
P. Pouyan, E. Amat, A. Rubio, S. Hamdioui,
Resistive Random Access Memory Variability and Its Mitigation Schemes
(February 2017),
Journal of Low Power Electronics (JOLPE), volume 13, issue 1
[Journal Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, M Alfailakawi,
Non-Volatile Look-up Table Based FPGA Implementations
(December 2016),
11th IEEE International Design & Test Symposium (IDT 2016), 18-20 December 2016, Hammamet, Tunisia
[Conference Proceedings]
A. Scionti, S. Mazumdar, S. Di Carlo, S. Hamdioui,
SIERRA - Simulation environment for memory redundancy algorithms
(December 2016),
Simulation Modelling Practice and Theory, volume 69
[Journal Paper]
G. Ch Sirakoulis, S. Hamdioui,
Editorial Note on Memristor Models, Circuits and Architectures
(December 2016),
International Journal of Unconventional Computing (IJUC), volume 12, issue 4
[Journal Paper]
D.H.P. Kraak, I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene,
On Mitigating Sense Amplifier Offset Voltage Degradation
(November 2016),
First IEEE International Workshop on Automotive Reliability & Test (ART Workshop 2016), 17-18 November 2016, Fort Worth, USA
[Conference Paper]
P. Pouyan, E. Amat, S. Hamdioui, A. Rubio,
RRAM Variability and Its Mitigation Schemes
(September 2016),
PATMOS & VARI 2016 (PATMOS & VARI 2016), 21-23 September 2016, Bremen, Germany
, Best Paper Award
[Conference Proceedings]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels,
CIM Architecture Communication Schemes
(September 2016),
The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (IMISCET 2016), 11 September 2016, Haifa, Israel
[Conference Paper]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels,
CIMx: Computation in-Memory Architecture Based on Resistive Devices
(August 2016),
15th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2016), 23-25 August 2016, Dresden, Germany
[Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Synthesizing HDL to memristor technology: A generic framework
(July 2016),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China
[Conference Paper]
M.A.B. Haron, J. Yu, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture
(July 2016),
International Conference on High Performance Computing & Simulation (HPCS 2016), 18-22 July 2016, Innsbruck, Austria
, Outstanding Paper Runner-up Award
[Conference Paper]
J. Yu, R. Nane, M.A.B. Haron, S. Hamdioui, H. Corporaal, K.L.M. Bertels,
Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures
(July 2016),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China
, Best Student Paper Award
[Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene,
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero- and Run-time Variability
(July 2016),
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), 11-13 July 2016, Pittsburgh, U.S.A.
, Best Paper Award
[Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene,
Read Path Degradation Analysis in SRAM
(May 2016),
IEEE European Test Symposium (ETS 2016), 24-27 May 2016, Amsterdam, The Netherlands
[Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Boolean Logic Gate Exploration for Memristor Crossbar
(April 2016),
11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2016), 12-14 april 2016, Istanbul, Turkey
[Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor,
Comparative BTI Analysis for Various Sense Amplifier Designs
(April 2016),
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 20-22 April 2016, Košice, Slovakia
[Conference Proceedings]
A Gebregiorgis, F Oboril, M Baradaran Tahoori, S. Hamdioui,
Instruction cache aging mitigation through Instruction Set Encoding
(March 2016),
17th International Symposium on Quality Electronic Design (ISQED 2016), 14-16 March 2016, Santa Clara, USA
[Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels,
CIM Based Parallel Adder Implementations and Evaluations
(January 2016),
Workshop on Memristor Technology, Design, Automation and Computing (MemTDAC 2016), 20 January 2016, Prague, Czech republic
[Conference Paper]
I Vourkas, D Stathis, G. Ch Sirakoulis, S. Hamdioui,
Alternative Architectures towards Reliable Memristive Crossbar Memories
(January 2016),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 24, issue 1
[Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor,
BTI Analysis of SRAM Write Driver
(December 2015),
10th IEEE International Design & Test Symposium (IDT 2015), 14-16 December 2015, Dead Sea, Jordan
[Conference Proceedings]
M Ottavi, S Pontarelli, D. Gizopoulos, C Bolchini, M K. Michael, L Anghel, M Baradaran Tahoori, A M. Paschalis, P Reviriego, O Bringmann, V Izosimov, H A. R. Manhaeve, C. Strydis, S. Hamdioui,
Dependable Multicore Architectures at Nanoscale: The View From Europe
(November 2015),
IEEE Design & Test of Computers (D&ToC)
[Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene,
Comparative BTI Impact for SRAM Cell and Sense Amplifier Designs
(November 2015),
MEDIAN Finale - Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2015), 10-11 November 2015, Tallinn, Estonia
[Conference Proceedings]
A Gebregiorgis, M Ebrahimi, S Kiamehr, F Oboril, S. Hamdioui, M Baradaran Tahoori,
Aging mitigation in memory arrays using selfcontrolled bit-flipping technique
(November 2015),
20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), 19-22 January 2015, Tokyo, Japan
[Conference Proceedings]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels,
Memristor: The Enabler of Computation-in-Memory Architecture for Big-Data
(November 2015),
International Conference on Memristive Systems (MEMRISYS 2015), 8 - 10 November 2015, Paphos, Cyprus
[Conference Proceedings]
L Brasca, M Sonza Reorda, S. Hamdioui,
SW-based transparent in-field memory testing
(November 2015),
16th IEEE Latin-American Test Symposium (LATS 2015), 25-27 March 2015, Puerto Vallarta, Mexico
[Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Fast Boolean Logic Mapped on Memristor Crossbar
(October 2015),
33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA
, Best Paper Award
[Conference Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Interconnect Networks for Memristor Crossbar
(July 2015),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA
[Conference Proceedings]
H.A. Du Nguyen, L. Xie, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels,
Computation-In-Memory Based Parallel Adder
(July 2015),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
(June 2015),
ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 20, issue 2
[Journal Paper]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen,
Post-Bond Interconnect Test and Diagnosis for 3D Memory Stacked on Logic
(May 2015),
IEEE Transactions on Computers (TC), issue 99
[Journal Paper]
Y Sfikas, Y Tsiatouhas, M. Taouil, S. Hamdioui,
On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect
(May 2015),
20th IEEE European Test Symposium (ETS 2015), 25-29 May 2015, Cluj-Napoca, Romania
[Conference Proceedings]
C Papameletis, B. Keller, V. Chickermane, S. Hamdioui, E.J. Marinissen,
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers
(April 2015),
IEEE Design & Test of Computers (D&ToC), volume 32, issue 4
[Journal Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor,
Integral Impact of BTI and Voltage Temperature Variation on SRAM Sense Amplifier
(April 2015),
IEEE VLSI Test Symposium (VTS 2015), 27-29 April 2015, Napa, USA
[Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, S. Cosemans, P Weckx, P. Raghavan, F. Catthoor,
Comparative Analysis of R-D and Atomistic Trap-Based BTI models on SRAM Sense Amplifier
(April 2015),
Design and Technology of Integrated Systems in the Nanoscale Era (DTIS 2015), 21-23 April 2015, Naples, Italy
, Best Paper Award
[Conference Proceedings]
A.M.M.O. Cortez, S. Hamdioui, A. Kaichouhi, V. van der Leest, R. Maes, G.J. Schrijen,
Intelligent Voltage Ramp-up Time Adaptation for Temperature Noise Reduction on Memory-based PUF Systems
(April 2015),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 34, issue 7
, DOI: 10.1109/TCAD.2015.2422844
[Journal Paper]
S. Hamdioui, L. Xie, H.A. Du Nguyen, M. Taouil, K.L.M. Bertels,
Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications
(March 2015),
18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France
[Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor,
BTI Analysis for High Performance and Low power SRAM Sense Amplifier
(March 2015),
4th Workshop On Manufacturable and Dependable Multicore Architectures (MEDIAN 2015), 13 March 2015, Grenoble, France
[Conference Paper]
A.M.M.O. Cortez, S. Hamdioui, G. Di Natale, M.-L. Flottes, B. Rouzeyre,
Hierarchical Secure DfT
(March 2015),
Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2015), 13 March 2015, Grenoble, France
[Conference Paper]
A.M.M.O. Cortez, S. Hamdioui, R. Ishihara,
Design Dependent SRAM PUF Robustness Analysis
(March 2015),
16th IEEE Latin-American Test Symposium (LATS 2015), 25-27 March 2015, Puerto Vallarta, Mexico
, DOI: 10.1109/LATW.2015.7102498
[Conference Paper]
S. Hamdioui, M. Taouil, N.Z.B. Haron,
Testing Open Defects in Memristor-Based Memories
(January 2015),
IEEE Transactions on Computers (TC), volume 64, issue 1
[Journal Paper]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale,
Testing Methods for PUF-Based Secure Key Storage Circuits
(October 2014),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 30, issue 5
, Digital Object Identifier (DOI): 10.1007/s10836-014-5471-7
[Journal Paper]
E.J. Marinissen, B de Wachter, K Smith, J Kiesewetter, M. Taouil, S. Hamdioui,
Direct Probing on Large-Array Fine-Pitch Micro-Bumps of a Wide-I/O Logic-Memory Interface.
(October 2014),
International Test Conference (ITC 2014), 21-23 October 2014, Seattle, USA
[Conference Proceedings]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale,
Secure Test Method for Fuzzy Extractor
(September 2014),
Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands
[Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor,
Impact of BTI on SRAM Sense Amplifier in the Presence of Temperature and Process Variation
(September 2014),
Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands
[Conference Proceedings]
P. D Joshi, S. Hamdioui,
Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures
(July 2014),
IEEE 15th International Conference on High Performance Switching and Routing (HPSR 2014), 1-4 July 2014, Vancouver, Canada
[Conference Proceedings]
Y Sfikas, Y Tsiatouhas, S. Hamdioui,
Layout-Based Refined NPSF Model for DRAM Characterization and Testing
(June 2014),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 22
[Journal Paper]
S. Hamdioui, H Aziza, G. Ch Sirakoulis,
Memristor based memories: Technology, design and test
(May 2014),
IEEE 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2014), 6-8 May 2014, Santorini, Greece
[Conference Proceedings]
S. Hamdioui,
3D/ 2.5D stacked IC cost modeling and test flow selection
(May 2014),
IEEE 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2014), 6-8 May 2014, Santorini, Greece
[Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik,
Quality versus Cost Analysis for 3D Stacked ICs
(April 2014),
32nd IEEE VLSI Test Symposium (VTS 2014), 13-17 April 2014, Napa, USA
[Conference Proceedings]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen,
Interconnect Test for 3D Stacked Memory-on-Logic
(March 2014),
Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany
[Conference Proceedings]
S. Hamdioui, G. Di Natale, G van Battum, J Danger, F Smailbegovic, M Tehranipoor,
Hacking and Protecting IC Hardware
(March 2014),
Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany
[Conference Paper]
H. Kukner, M.S. Khan, S. Hamdioui, P. Raghavan, F. Catthoor,
Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates
(March 2014),
IEEE Transactions on Reliability (TR), volume 14, issue 1
[Journal Paper]
A.M.M.O. Cortez, G. Roelofs, S. Hamdioui, G. Di Natale,
Testing PUF-based Secure Key Storage Circuits
(March 2014),
Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany
[Conference Paper]
M.S. Khan, I.O. Agbo, S. Hamdioui, H. Kukner, B Kaczer, P. Raghavan, F. Catthoor,
Bias Temperature Instability analysis of FinFET based SRAM cells
(March 2014),
Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany
[Conference Proceedings]
I.O. Agbo, M.S. Khan, S. Hamdioui,
BTI Impact on SRAM Sense Amplifier
(December 2013),
8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco
[Conference Paper]
L.M. Ciganda, P. Bernardi, M. Sonza Reorda, S. Hamdioui,
An efficient method for the test of embedded memory cores during the operational phase
(November 2013),
22nd Asian Test Symposium (ATS 2013), 18-21 November 2013, Yilan, Taiwan
[Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik,
Using 3D-COSTAR for 2.5D Test Cost Optimization
(October 2013),
IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik,
Impact of Mid-Bond Testing in 3D Stacked ICs
(October 2013),
16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA
[Conference Paper]
A.M.M.O. Cortez, V. van der Leest, R. Maes, G.J. Schrijen, S. Hamdioui,
Adapting Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs
(June 2013),
IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2013), 2-3 June 2013, Austin, USA
[Conference Paper]
M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor,
Bias temperature instability analysis in SRAM decoder
(May 2013),
18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France
[Conference Paper]
C. Papameletis,, B. Keller, V. Chickermane, E.J. Marinissen, S. Hamdioui,
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
(May 2013),
18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France
[Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor,
GENERIC MARCH ELEMENT BASED MEMORY BUILT-IN SELF TEST
(April 2013),
filed in USA
[Patent]
S. Hamdioui, D. Gizopoulos, G. Guido, M. Nicolaidis, A. Grasset, P. Bonnot,
Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes
(March 2013),
Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France
[Conference Proceedings]
A.M.M.O. Cortez, S. Hamdioui, V. van der Leest, R. Maes, G.J. Schrijen,
Noise Reduction on Memory-based PUFs
(March 2013),
1st Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2013), 30-31 May 2013, Avignon, France
[Conference Paper]
M. Lefter, G.R. Voicu, M. Taouil, M. Enachescu, S. Hamdioui, S.D. Cotofana,
Is TSV-based 3D Integration Suitable for Inter-die Memory Repair?
(March 2013),
Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France
[Conference Paper]
M.S. Khan, S. Hamdioui,
Variability and Reliability Analyses in SRAM Decoder
(January 2013),
4th Workshop on Design for Reliability (DFR 2012), 23-25 January 2012, Paris, France
[Conference Paper]
S. Hamdioui,
Testing Embedded Memories: A Survey
(January 2013),
Mathematical and Engineering Methods in Computer Science, issue Springer Berlin Heidelberg
[Journal Paper]
M.S. Khan, S. Hamdioui, M. Taouil, H. Kukner, P. Raghavan, F. Catthoor,
Impact of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder Reliablity
(December 2012),
International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar
[Conference Proceedings]
M. Taouil, M. Lefter, S. Hamdioui,
Exploring Test Opportunities for Memory and Interconnects in 3D ICs
(December 2012),
International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik,
3D-COSTAR: A Cost Model For 3D Stacked ICs
(November 2012),
Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012), 8-9 November 2012, Anaheim, USA
[Conference Proceedings]
A.M.M.O. Cortez, V. van der Leest, G.J. Schrijen, S. Hamdioui,
Investigation of Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs
(October 2012),
ICT.OPEN 2012 (ICT.OPEN 2012), 22-23 October 2012, Rotterdam, The Netherlands
[Conference Paper]
M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor,
Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis
(October 2012),
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 3-5 October 2012, Austin, USA
[Conference Paper]
A.M.M.O. Cortez, A. Dargar, G.J. Schrijen, S. Hamdioui,
Modeling SRAM Start-Up Behavior for Physical Unclonable Functions
(October 2012),
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 3-5 October 2012, Austin, USA
, Best Student Paper Award
[Conference Paper]
M. Taouil, S. Hamdioui,
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
(August 2012),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 28 , issue 4
[Journal Paper]
M.S. Khan, S. Hamdioui,
Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates
(June 2012),
1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012), 1 June 2012, Annecy, France
[Conference Paper]
M. Taouil, S. Hamdioui,
On Optimizing Test Cost for Wafer-to-Wafer 3D Stacked ICs
(May 2012),
7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 16-18 May 2012, Tunis, Tunisia
[Conference Paper]
M.S. Khan, S. Hamdioui, H. Kukner, F. Catthoor, P. Raghavan,
BTI Impacts on Logical Gates in Nano-scale CMOS Technology
(April 2012),
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), 18-20 April 2012, Tallinn, Estonia
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
DfT Schemes for Resistive Open Defects in RRAMs
(March 2012),
Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), 12-16 March 2012, Dresden, Germany
[Conference Paper]
M.S. Khan, S. Hamdioui, F. Catthoor,
Comparative BTI Analysis in Nano-scale Circuits Lifetime
(January 2012),
4th Workshop on Design for Reliability (DFR 2012), 23-25 January 2012, Paris, France
[Conference Paper]
M.S. Khan, S. Hamdioui,
ReverseAge: an Online NBTI Combating Technique Using Time Borrowing
(December 2011),
IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon
[Conference Paper]
M. Taouil, S. Hamdioui, C.I.M. Beenakker, E.J. Marinissen,
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
(December 2011),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 28, issue 1
[Journal Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
On Modeling and Optimizing Cost in 3D Stacked-ICs
(December 2011),
IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon
[Conference Paper]
S. Hamdioui, M. Taouil,
Yield Improvement and Test Cost Optimization for 3D Stacked ICs
(November 2011),
20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India
[Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui,
Testing for Parasitic Memory Effect in SRAMs
(November 2011),
20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
On Defect Oriented Testing for Hybrid CMOS/memristor Memory
(November 2011),
20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India
[Conference Paper]
M.S. Khan, S. Hamdioui, N.Z.B. Haron, F. Catthoor,
NBTI Monitoring and Design for Reliability in Nanoscale Circuits
(October 2011),
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011), 3-5 October 2011, Vancouver, Canada
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
Test Cost Modeling for 3D-Stacked ICs
(September 2011),
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 22-23 September 2011, Anaheim, USA
[Conference Paper]
M.S. Khan, S. Hamdioui,
Modeling and Mitigating NBTI in Nanoscale Circuits
(July 2011),
17th IEEE International On-Line Testing Symposium (IOLTS), 13-15 July 2011, Athens, Greece
[Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui,
Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs
(May 2011),
16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway
[Conference Paper]
M. Taouil, S. Hamdioui,
Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
(May 2011),
16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway
[Conference Paper]
A.J. van de Goor, H. Kukner, S. Hamdioui,
Optimizing Memory BIST Address Generator Implementations
(April 2011),
6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece
, Best Paper Award
[Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell,
Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs
(April 2011),
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany
[Conference Paper]
M. Taouil, S. Hamdioui,
Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost
(April 2011),
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?
(April 2011),
6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories
(March 2011),
Design, Automation and Test in Europe (DATE 2011), 14-18 March 2011, Grenoble, France
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
(January 2011),
ACM Journal on Emerging Technologies in Computing Systems (JETC), volume 7, issue 1
, article 4
[Journal Paper]
N.Z.B. Haron, S. Hamdioui,
On Correcting Cluster Errors in Nanoelectronic Memories
(January 2011),
3rd HiPEAC Workshop on Design for Reliability (DFR 2011), 23 January 2011, Heraklion, Greece
[Conference Paper]
A.J. van de Goor, S. Hamdioui, H. Kukner,
Generic, Orthogonal and Low-Cost March Element-based Memory BIST
(January 2011),
IEEE International Test Conference (IEEE ITC), 20-22 Sept, Anaheim, CA, USA
[Conference Proceedings]
M.S. Khan, S. Hamdioui,
NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation
(January 2011),
3rd HiPEAC Workshop on Design for Reliability (DFR 2011), 23 January 2011, Heraklion, Greece
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
Test Cost Analysis for 3D Die-to-Wafer Stacking
(December 2010),
19th IEEE Asian Test Symposium (ATS 2010), 1-4 December 2010, Shanghai, China
[Conference Paper]
A.J. van de Goor, S. Hamdioui,
MBIST Architecture Framework based on Orthogonal Constructs
(December 2010),
5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE
[Conference Paper]
N.Z.B. Haron, S. Hamdioui, Z. Ahyadi,
ECC Design for Fault-Tolerant Crossbar Memories: A Case Study
(December 2010),
5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE
[Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen,
Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking
(November 2010),
First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 4-5 November 2010, Austin, USA
[Conference Paper]
M. Taouil, S. Hamdioui, J. Verbree, E.J. Marinissen,
On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs
(November 2010),
IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA
[Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui,
Detecting Memory Faults in the Presence of Bit Line Coupling in SRAM Devices
(November 2010),
IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories
(October 2010),
25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2010), 6-8 October 2010, Kyoto, Japan
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Mitigating Defective CMOS to Non-CMOS Vias in CMOS/Molecular Memories
(August 2010),
10th IEEE International Conference on Nanotechnology (NANO 2010), August 2010, Seoul, Korea
, Certificate of Merit
[Conference Paper]
M.S. Khan, S. Hamdioui,
Temperature Dependence of NBTI Induced Delay
(July 2010),
16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July 2010, Corfu, Greece
[Conference Paper]
A.J. van de Goor, C. Jung, S. Hamdioui, G.N. Gaydadjiev,
Low-cost, Customized and Flexible SRAM MBIST Engine
(April 2010),
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria
[Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui,
Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs
(April 2010),
28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA
[Conference Paper]
A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev,
Using a CISC microcontroller to test embedded memories
(April 2010),
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), 14-16 April 2010, Vienna, Austria
[Conference Paper]
A.J. van de Goor, G.N. Gaydadjiev, S. Hamdioui,
Memory Testing with a RISC Microcontroller
(March 2010),
Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany
[Conference Paper]
M.S. Khan, S. Hamdioui,
NBTI Modeling in the Framework of Temperature Variation
(March 2010),
Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany
[Conference Paper]
M.S. Khan, S. Hamdioui,
Trends and challenges of SRAM reliability in the nano-scale era
(March 2010),
5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS 2010), 23-25 March 2010, Hammamet, Tunisia
[Conference Paper]
M.S. Khan, S. Hamdioui,
Temperature Impact on NBTI Modeling in the Framework of Technology Scaling
(January 2010),
2nd HiPEAC Workshop on Design for Reliability (DFR 2010), 24 January 2010, Pisa, Italy
[Conference Paper]
Z. Al-Ars, S. Hamdioui,
Non-Algorithmic Stress Optimization Using Simulation for DRAMs
(November 2009),
4th International Design and Test Workshop (IDT 2009), 15-17 November 2009, Riyadh, Saudi Arabia
[Conference Paper]
Z. Al-Ars, S. Hamdioui,
Fault Diagnosis Using Test Primitives in Random Access Memories
(November 2009),
18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan
[Conference Paper]
A.J. van de Goor, S. Hamdioui, G.N. Gaydadjiev,
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
(November 2009),
18th Asian Test Symposium (ATS 2009), 23-26 November 2009, Taichung, Taiwan
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories
(October 2009),
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2009), 7-9 October 2009, Chicago, USA
[Conference Paper]
D. Borodin, B.H.H. Juurlink, S. Hamdioui, S. Vassiliadis,
Instruction-Level Fault Tolerance Configurability
(October 2009),
Journal of Signal Processing Systems (JSPS), volume 57, issue 1
[Journal Paper]
N.Z.B. Haron, S. Hamdioui,
Residue-Based Code for Reliable Hybrid Memories
(July 2009),
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009), 30-31 July 2009, San Fransisco, USA
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Fault Tolerance Architecture for Reliable Hybrid CMOS/Nanodevice Memories
(May 2009),
14th IEEE European Test Symposium (ETS 2009), 25-29 May 2009, Sevilla, Spain
[Conference Paper]
S. Hamdioui, Z. Al-Ars,
Scan More with Memory Scan Test
(April 2009),
4th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2009), 6-9 April 2009, Cairo, Egypt
[Conference Paper]
N.Z.B. Haron, S. Hamdioui, S.D. Cotofana,
Emerging Non-CMOS Nanoelectronic Devices - What Are They?
(January 2009),
4th IEEE International Conference of Nano/Micro Engineered & Molecular Systems (IEEE-NEMS 2009), 5-8 January 2009, Shenzhen, China
[Conference Paper]
Z. Al-Ars, S. Hamdioui,
Evaluation of SRAM Faulty Behavior Under Bit Line Coupling
(December 2008),
3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia
[Conference Paper]
S. Hamdioui, Z. Al-Ars,
Efficient Tests and DFT for RAM Address Decoder Delay Faults
(December 2008),
3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Why is CMOS scaling coming to an END?
(December 2008),
3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia
[Conference Paper]
K. Yamasaki, S. Hamdioui, Z. Al-Ars, A.J. van Genderen, G.N. Gaydadjiev,
High Quality Simulation Tool for Memory Redundancy Algorithms
(November 2008),
19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands
[Conference Paper]
M.S. Khan, S. Hamdioui, N.Z.B. Haron,
CMOS scaling impacts on Reliability, What do we understand?
(November 2008),
19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands
[Conference Paper]
N.Z.B. Haron, S. Hamdioui,
Emerging Crossbar-based Hybrid Nanoarchitectures for Future Computing Systems
(November 2008),
IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia
[Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero,
BIST Enhancement for Detecting Bit/Byte Write Enable Faults in SOC SRAMs
(November 2008),
IEEE International Conference on Signals, Circuits and Systems (SCS 2008), 7-9 November 2008, Hammamet, Tunisia
[Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller,
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs
(October 2008),
IEEE International Test Conference (ITC 2008), 26-31 October 2008, Santa Clara, USA
[Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, S. Vassiliadis,
Test Set Development for Cache Memory in Modern Microprocessors
(June 2008),
IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 16, issue 6
[Journal Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev,
Precise Identification of Memory Faults Using Electrical Simulation
(December 2007),
2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt
[Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, A.J. van de Goor,
An Investigation on Capacitive Coupling in RAM Address Decoders
(December 2007),
2nd International Design and Test Workshop (IDT 2007), 16-18 December 2007, Cairo, Egypt
[Conference Paper]
S. Hamdioui, A. Orailoglu,
Proceedings of IEEE DTIS07
(September 2007),
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco
[Conference Proceedings]
K.L.M. Bertels, S.D. Cotofana, G.N. Gaydadjiev, K.G.W. Goossens, S. Hamdioui, B.H.H. Juurlink, A.J. van Genderen, S. Wong,
The Future of Computing, essays in memory of Stamatis Vassiliadis
(September 2007),
Published by Computer Engineering Laboratory, TU Delft
[Book]
Z. Al-Ars, S. Hamdioui,
Automatic Analysis of Memory Faulty Behavior in Defective Memories
(September 2007),
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), 2-5 September 2007, Rabat, Morocco
[Conference Paper]
S. Hamdioui, Z. Al-Ars, J. Jimenez, J. Calero,
PPM Reduction on Embedded Memories in System on Chip
(May 2007),
12th IEEE European Test Symposium (ETS 2007), 20-24 May 2007, Freiburg, Germany
[Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev,
Optimizing Test Length for Soft Faults in DRAM Devices
(May 2007),
25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, USA
[Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev,
Manifestation of Precharge Faults in High Speed DRAM Devices
(April 2007),
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2007), 11-13 April 2007, Krakow, Poland
[Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi,
Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs
(December 2006),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12
[Journal Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor,
Opens and Delay Faults in CMOS RAM Address Decoder
(December 2006),
IEEE Transactions on Computers (TC), volume 55, issue 12
[Journal Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes,
Comparison of Static and Dynamic Faults in 65nm Memory Technology
(November 2006),
1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE
[Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev,
Using Linear Tests for Transient Faults in DRAMs
(November 2006),
1st IEEE International Design and Test Workshop (IDT 2006), 19-20 November 2006, Dubai, UAE
[Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev, J. Vollrath,
DRAM-Specific Space of Memory Tests
(October 2006),
IEEE International Test Conference (ITC 2006), 22-27 October 2006, Santa Clara, USA
[Conference Paper]
S. Hamdioui, Z. Al-Ars, L. Mhamdi, G.N. Gaydadjiev,
Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies
(September 2006),
International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006), 5-7 September 2006, Tunis, Tunesia
[Conference Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, J. Vollrath,
Bitline-Coupled Precharge Faults and Their Detection in Memory Devices
(May 2006),
11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK
[Conference Paper]
S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev, J.D. Reyes,
Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies
(May 2006),
11th IEE European Test Symposium (ETS 2006), 21-24 May 2006, Southampton, UK
[Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor,
Space of DRAM Fault Models and Corresponding Testing
(March 2006),
Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany
[Conference Paper]
S. Hamdioui, A.J. van de Goor, J.D. Reyes, M. Rodgers,
Memory Test Experiment: Industrial Results and Data
(January 2006),
IEE Proceedings - Computers and Digital Techniques, volume 153, issue 1
[Journal Paper]
Z. Al-Ars, S. Hamdioui, J. Vollrath,
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach
(December 2005),
14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India
[Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R. Wadsworth,
Impact of Stresses on the Fault Coverage of Memory Tests
(August 2005),
IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan
[Conference Paper]
S. Hamdioui, J.D. Reyes,
New Data-Background Sequences and Their Industrial Evaluation for Word-Oriented Random-Access Memories
(June 2005),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 24, issue 6
[Journal Paper]
Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor,
Framework for Fault Analysis and Test Generation in DRAMs
(March 2005),
Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany
[Conference Paper]
S. Hamdioui, J.D. Reyes, Z. Al-Ars,
Evaluation of Intra-Word Faults in Word-Oriented RAMs
(November 2004),
13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan
[Conference Paper]
A.J. van de Goor, S. Hamdioui, R. Wadsworth,
Detecting Faults in Peripheral Circuits and an Evaluation of SRAM Tests
(October 2004),
International Test Conference (ITC 2004), 26-28 October 2004, Charlotte, USA
[Conference Paper]
S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor,
The State-of-the-art and Future Trends in Testing Embedded Memories
(August 2004),
12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA
[Conference Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars,
The Effectiveness of Scan Test and Its New Variants
(August 2004),
12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA
[Conference Paper]
S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor,
Memory Fault Modeling Trends: A Case Study
(June 2004),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 20, issue 3
[Journal Paper]
A.J. van de Goor, S. Hamdioui, Z. Al-Ars,
Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens
(May 2004),
9th IEEE European Test Symposium (ETS 2004), 23-26 May 2004, Corsica, France
[Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers,
Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results
(May 2004),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 23, issue 5
[Journal Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor,
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs
(April 2004),
22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa, USA
[Conference Paper]
S. Hamdioui,
Testing Static Random Access Memories
(March 2004),
Published by Kluwer Academic Publishers
[Book]
S. Hamdioui, G.N. Gaydadjiev, A.J. van de Goor,
A Fault Primitive Based Analysis of Dynamic Memory Faults
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers,
March SL: A Test For All Static Linked Memory Faults
(November 2003),
12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China
[Conference Paper]
S. Hamdioui, G.N. Gaydadjiev,
Future Challenges in Memory Testing
(November 2003),
14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands
[Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor,
A Fault Primitive Based Analysis of Linked Faults in RAMs
(July 2003),
11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA
[Conference Paper]
S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor,
Importance of Dynamic Faults for New SRAM Technologies
(May 2003),
8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands
[Conference Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers,
Detecting intra-word faults in word-oriented memories
(April 2003),
21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, USA
[Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers,
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
(April 2003),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2
[Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers,
March SS: A test for all static simple RAM faults
(July 2002),
10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France
[Conference Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers,
DPM Reduction On Dual Port Caches
(May 2002),
7th IEEE European Test Workshop (ETW 2002), 26-29 May 2002, Corfu, Greece
[Conference Paper]
S. Hamdioui, A.J. van de Goor,
Efficient Tests for Realistic Faults in Dual-Port Memories
(May 2002),
IEEE Transactions on Computers (TC), volume 51, issue 5
[Journal Paper]
S. Hamdioui, A.J. van de Goor,
Thorough Tesing Any Multi-Port Memory with Linear Tests
(February 2002),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 21, issue 2
[Journal Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor,
Testing static and dynamic faults in random access memories
(January 2002),
20th IEEE VLSI Test Symposium (VTS 2002), 28 April - 2 May 2002, Monterey, USA
[Conference Paper]
S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers,
Detecting unique faults in multi-port SRAMs
(November 2001),
10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan
[Conference Paper]
S. Hamdioui, A.J. van de Goor, D. Eastwick, M. Rodgers,
Realistic fault models and test procedure for multi-port SRAMs
(August 2001),
9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, USA
[Conference Paper]
S. Hamdioui,
Testing Multi-Port Memories: Theory and Practice
(April 2001),
, Outstanding Dissertation Award
[Phd Thesis]
S. Hamdioui, A.J. van de Goor,
An experimental analysis of spot defects in SRAMs: realistic fault models and test
(December 2000),
9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan
[Conference Paper]
S. Hamdioui, A.J. van de Goor,
Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy
(October 2000),
Journal of Electronic Testing: Theory and Applications (JETTA), volume 16, issue 5
[Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, D. Eastwick,
March tests for realistic faults in two-port memories
(August 2000),
8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, USA
[Conference Paper]