A. F Lorenzon

NameA. F Lorenzon
First Name
E-mailaflorenzon@inf.ufrgs.br
Author TypeExternal
AffiliationUFRGS, Porto Alegre, Brazil

Publications

J.J. Hoozemans, A. F Lorenzon, A.C.S. Beck, S. Wong, Improved dynamic cache sharing for communicating threads on a runtime-adaptable processor 1601_improved_dynamic_cache_sharing_for_communicating_threads_on.pdf (January 2017), 11th HiPEAC Workshop on Reconfigurable Computing (WRC2017), 23-1-2017, Stockholm, Sweden [Conference Paper]
A. L. Sartor, A. F Lorenzon, L. Carro, F. Kastensmidt, S. Wong, A.C.S. Beck, Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors 1598_exploiting_idle_hardware_to_provide_low_overhead_fault_tole.pdf (January 2017), ACM Journal on Emerging Technologies in Computing Systems (JETC), volume 13, issue 2 [Journal Paper]
A.A.C. Brandon, J.J. Hoozemans, J. Van Straten, A. F Lorenzon, A. L. Sartor, A.C.S. Beck, S. Wong, A Sparse VLIW Instruction Encoding Scheme Compatible with Generic Binaries 1518_a_sparse_vliw_instruction_encoding_scheme_compatible_with_g.pdf (December 2015), 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015), 7-9 December 2015, Mayan Riviera, Mexico [Conference Paper]
A. L. Sartor, A. F Lorenzon, L. Carro, F. Kastensmidt, S. Wong, A.C.S. Beck, A Novel Phase-based Low Overhead Fault Tolerance Approach for VLIW Processors 1485_a_novel_phasebased_low_overhead_fault_tolerance_approach_f.pdf (July 2015), IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 08-10 July 2015, Montpellier, France [Conference Paper]