P. Celinski, D. Abbott, S.D. Cotofana, Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic (September 2004), 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), 15-17 September 2004, Santorini, Greece [Conference Paper]

P. Celinski, S.F. Al-Sarawi, D. Abbott, S.D. Cotofana, S. Vassiliadis, Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach (February 2004), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 19-20 February 2004, Lafayette, USA [Conference Paper]

P. Celinski, S.D. Cotofana, D. Abbott, Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]

P. Celinski, S.D. Cotofana, D. Abbott, A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]

P. Celinski, S.D. Cotofana, D. Abbott, Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]

P. Celinski, S.D. Cotofana, J.F. Lopez, S.F. Al-Sarawi, D. Abbott, State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications (May 2003), SPIE International Symposium on Microtechnologies for the New Millennium, 19-21 May 2003, San Agustín, Gran Canaria, Spain , Invited Paper [Conference Paper]

P. Celinski, S.D. Cotofana, D. Abbott, Threshold Logic Parallel Counters for 32-bit Multipliers (December 2002), International Symposium on Smart Materials, Nano- and Micro-Smart Systems, 2-4 December 2002, Melbourne, Australia [Conference Paper]