I. Schanstra

NameI. Schanstra
First Name
Author TypeExternal


Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs 911_influence_of_bit_line_twisting_on_the_faulty_behavior_of_dra.pdf (August 2004), 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, USA [Conference Paper]
I. Schanstra, A.J. van de Goor, Consequences of RAM bitline twisting for test coverage 1047_consequences_of_ram_bitline_twisting_for_test_coverage.pdf (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]
I. Schanstra, A.J. van de Goor, Logical and topological testing of scrambled RAMs (February 2003), 4th IEEE Latin American Test Workshop (LATW 2003), 16-19 February 2003, Natal, Brazil [Conference Paper]
A.J. van de Goor, I. Schanstra, Address and data scrambling: causes and impact on memory tests 1162_address_and_data_scrambling_causes_and_impact_on_memory_te.pdf (January 2002), 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 200, Christchurch, New Zealand [Conference Paper]