C. Dan, Hardware Algorithms for Tile-Based Real-Time Rendering (May 2012), [Phd Thesis]

M.D. Padure, S.D. Cotofana, C. Dan, S. Vassiliadis, M. Bodea, Compact Delay Modeling of Latch-based Threshold Logic Gates (October 2002), International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania , Best Paper Award [Conference Paper]

M.D. Padure, S.D. Cotofana, S. Vassiliadis, C. Dan, M. Bodea, A low-power threshold logic family (September 2002), 9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia [Conference Paper]

M.D. Padure, S.D. Cotofana, C. Dan, M. Bodea, S. Vassiliadis, A new latch-based threshold logic family (October 2001), International Semiconductor Conference (CAS 2001), 9-13 October 2001, Sinaia, Romania [Conference Paper]