M.D. Padure

NameM.D. Padure
First NameMarius
E-mail
Author TypeExternal
AffiliationTU Delft

Publications

K.C. Li, M.D. Padure, S.D. Cotofana, neuronMOS enhanced Differential Current-Switch Threshold Logic Gates 872_neuronmos_enhanced_differential_currentswitch_threshold_log.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, CMOS Implementation of Generalized Threshold Functions (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, Design and Experimental Results of a CMOS Flip-Flop Featuring Embedded Threshold Logic (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, A CMOS Flip-flop Featuring Embedded Threshold Logic Functions 1133_a_cmos_flipflop_featuring_embedded_threshold_logic_functio.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, High-speed Hybrid Threshold-Boolean Logic 1134_highspeed_hybrid_thresholdboolean_logic.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
M.D. Padure, S.D. Cotofana, C. Dan, S. Vassiliadis, M. Bodea, Compact Delay Modeling of Latch-based Threshold Logic Gates 1160_compact_delay_modeling_of_latchbased_threshold_logic_gates.pdf (October 2002), International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania , Best Paper Award [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, C. Dan, M. Bodea, A low-power threshold logic family 1090_a_lowpower_threshold_logic_family.pdf (September 2002), 9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, High-speed hybrid threshold-Boolean logic counters 1100_highspeed_hybrid_thresholdboolean_logic_counters.pdf (August 2002), 45th Midwest Symposium on Circuits and Systems (MWSCAS 2002), 4-7 August 2002, Tulsa, USA [Conference Paper]
M.D. Padure, S.D. Cotofana, C. Dan, M. Bodea, S. Vassiliadis, A new latch-based threshold logic family 1231_a_new_latchbased_threshold_logic_family.pdf (October 2001), International Semiconductor Conference (CAS 2001), 9-13 October 2001, Sinaia, Romania [Conference Paper]