R. Ferreira, L. Rocha, A. Santos, J. Nacif, S. Wong, L. Carro, A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal (April 2015), ACM Transactions on Reconfigurable Technology and Systems (TRETS), volume 8, issue 2 [Journal Paper]

R. Ferreira, W Denver, M Pereira, S. Wong, C. A. L. Arthur Lang Lisbôa, L. Carro, A Dynamic Modulo Scheduling with Binary Translation: Loop Optimization with Software Compatibility (January 2015), Journal of Signal Processing Systems (JSPS) , http://link.springer.com/article/10.1007/s11265-015-0974-8 [Journal Paper]

R. Ferreira, W Denver, M Pereira, J Quadros, L. Carro, S. Wong, A Run-Time Modulo Scheduling by using a Binary Translation Mechanism (July 2014), International Conference on Embedded Computer Systems: Architecture Modeling and Simulation (IC-SAMOS 2014), 14-17 July 2014 , Samos, Greece [Conference Paper]

R. Ferreira, L. Rocha, A. Santos, J. Nacif, S. Wong, L. Carro, A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS (September 2013), 23nd International Conference on Field Programmable Logic and Applications (FPL 2013), 2-4 September 2013, Porto, Portugal , FPL Michael Servit Memorial (Best Paper) Award [Conference Paper]

R. Ferreira, V. Duarte, W. Meireles, M Pereira, L. Carro, S. Wong, A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained Reconfigurable Architectures (July 2013), International Conference on Embedded Computer Systems: Architecture Modeling and Simulation (IC-SAMOS 2013), 15-18 July 2013, Samos, Greece [Conference Paper]