J. Yu

NameJ. Yu
First Name
Author TypePhd Student


J. Yu, H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, Memristive Devices for Computation-In-Memory (March 2018), Design, Automation and Test in Europe (DATE 2018), 19-23 March 2018, Dresden, Germany [Conference Paper]
J. Yu, R. Nane, I. Ashraf, M. Taouil, S. Hamdioui, H. Corporaal, K.L.M. Bertels, Skeleton-based Synthesis Flow for Computation-In-Memory Architectures (October 2017), IEEE Transactions on Emerging Topics in Computing, volume PP, issue 99 , Pre-publish [Journal Paper]
L. Xie, H.A. Du Nguyen, J. Yu, A. Kaichouhi, M. Taouil, S. Hamdioui, Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing (July 2017), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), 3-5 July 2017, Bochum, Germany [Conference Proceedings]
J. Yu, T. Hogervorst, R. Nane, A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons 1609_a_domainspecific_language_and_compiler_for_computationin.pdf (May 2017), 27th ACM Great Lakes Symposium on VLSI (GLSVLSI 2017), 10-12 May 2017, Banff, Canada [Conference Paper]
L. Xie, H.A. Du Nguyen, J. Yu, M. Taouil, S. Hamdioui, On the Robustness of Memristor Based Logic Gates (April 2017), IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017, Dresden, Germany [Conference Proceedings]
H.A. Du Nguyen, L. Xie, J. Yu, M. Taouil, S. Hamdioui, Interconnect Networks for Resistive Computing Architectures (April 2017), 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), 4-6 April 2017, Palma de Mallorca, Spain [Conference Paper]
M.A.B. Haron, J. Yu, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels, Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture 1550_parallel_matrix_multiplication_on_memristorbased_computati.pdf (July 2016), International Conference on High Performance Computing & Simulation (HPCS 2016), 18-22 July 2016, Innsbruck, Austria , Outstanding Paper Runner-up Award [Conference Paper]
J. Yu, R. Nane, M.A.B. Haron, S. Hamdioui, H. Corporaal, K.L.M. Bertels, Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures 1544_skeletonbased_design_and_simulation_flow_for_computationi.pdf (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China , Best Student Paper Award [Conference Proceedings]