M. Taouil

NameM. Taouil
First NameMottaqiallah
E-mailM.Taouil@tudelft.nl
Author TypePostDoc
AffiliationTU Delft

Publications

D.H.P. Kraak, I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene, On Mitigating Sense Amplifier Offset Voltage Degradation 1590_on_mitigating_sense_amplifier_offset_voltage_degradation.pdf (November 2016), First IEEE International Workshop on Automotive Reliability & Test (ART Workshop 2016), 17-18 November 2016, Fort Worth, USA [Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, CIM Architecture Communication Schemes (September 2016), The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (IMISCET 2016), 11 September 2016, Haifa, Israel [Conference Paper]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels, CIMx: Computation in-Memory Architecture Based on Resistive Devices (August 2016), 15th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2016), 23-25 August 2016, Dresden, Germany [Conference Paper]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, Synthesizing HDL to memristor technology: A generic framework (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China [Conference Paper]
M.A.B. Haron, J. Yu, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels, Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture 1550_parallel_matrix_multiplication_on_memristorbased_computati.pdf (July 2016), International Conference on High Performance Computing & Simulation (HPCS 2016), 18-22 July 2016, Innsbruck, Austria , Outstanding Paper Runner-up Award [Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene, Quantification of Sense Amplifier Offset Voltage Degradation due to Zero- and Run-time Variability 1543_quantification_of_sense_amplifier_offset_voltage_degradatio.pdf (July 2016), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), 11-13 July 2016, Pittsburgh, U.S.A. , Best Paper Award [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, W Dehaene, Read Path Degradation Analysis in SRAM 1540_read_path_degradation_analysis_in_sram.pdf (May 2016), IEEE European Test Symposium (ETS 2016), 24-27 May 2016, Amsterdam, The Netherlands [Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Boolean Logic Gate Exploration for Memristor Crossbar (April 2016), 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2016), 12-14 april 2016, Istanbul, Turkey [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, Comparative BTI Analysis for Various Sense Amplifier Designs 1532_comparative_bti_analysis_for_various_sense_amplifier_design.pdf (April 2016), IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 20-22 April 2016, Košice, Slovakia [Conference Proceedings]
H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, K.L.M. Bertels, CIM Based Parallel Adder Implementations and Evaluations (January 2016), Workshop on Memristor Technology, Design, Automation and Computing (MemTDAC 2016), 20 January 2016, Prague, Czech republic [Conference Paper]
I. Ashraf, M. Taouil, K.L.M. Bertels, Memory Profiling for Intra-Application Data-Communication Quantification: A Survey 1515_memory_profiling_for_intraapplication_datacommunication_q.pdf (December 2015), 10th IEEE International Design & Test Symposium (IDT 2015), 14-16 December 2015, Dead Sea, Jordan [Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, F. Catthoor, BTI Analysis of SRAM Write Driver 1521_bti_analysis_of_sram_write_driver.pdf (December 2015), 10th IEEE International Design & Test Symposium (IDT 2015), 14-16 December 2015, Dead Sea, Jordan [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, P Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W Dehaene, Comparative BTI Impact for SRAM Cell and Sense Amplifier Designs 1516_comparative_bti_impact_for_sram_cell_and_sense_amplifier_de.pdf (November 2015), MEDIAN Finale - Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2015), 10-11 November 2015, Tallinn, Estonia [Conference Proceedings]
S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, K.L.M. Bertels, Memristor: The Enabler of Computation-in-Memory Architecture for Big-Data (November 2015), International Conference on Memristive Systems (MEMRISYS 2015), 8 - 10 November 2015, Paphos, Cyprus [Conference Proceedings]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Fast Boolean Logic Mapped on Memristor Crossbar 1505_fast_boolean_logic_mapped_on_memristor_crossbar.pdf (October 2015), 33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA , Best Paper Award [Conference Paper]
L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, Interconnect Networks for Memristor Crossbar (July 2015), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA [Conference Proceedings]
H.A. Du Nguyen, L. Xie, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels, Computation-In-Memory Based Parallel Adder 1497_computationinmemory_based_parallel_adder.pdf (July 2015), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), 8-10 July 2015, Boston, USA [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching (June 2015), ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 20, issue 2 [Journal Paper]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Post-Bond Interconnect Test and Diagnosis for 3D Memory Stacked on Logic (May 2015), IEEE Transactions on Computers (TC), issue 99 [Journal Paper]
Y Sfikas, Y Tsiatouhas, M. Taouil, S. Hamdioui, On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect (May 2015), 20th IEEE European Test Symposium (ETS 2015), 25-29 May 2015, Cluj-Napoca, Romania [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, Integral Impact of BTI and Voltage Temperature Variation on SRAM Sense Amplifier 1483_integral_impact_of_bti_and_voltage_temperature_variation_on.pdf (April 2015), IEEE VLSI Test Symposium (VTS 2015), 27-29 April 2015, Napa, USA [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, S. Cosemans, P Weckx, P. Raghavan, F. Catthoor, Comparative Analysis of R-D and Atomistic Trap-Based BTI models on SRAM Sense Amplifier 1482_comparative_analysis_of_rd_and_atomistic_trapbased_bti_mo.pdf (April 2015), Design and Technology of Integrated Systems in the Nanoscale Era (DTIS 2015), 21-23 April 2015, Naples, Italy , Best Paper Award [Conference Proceedings]
S. Hamdioui, L. Xie, H.A. Du Nguyen, M. Taouil, K.L.M. Bertels, Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications 1476_memristor_based_computationinmemory_architecture_for_data.pdf (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, BTI Analysis for High Performance and Low power SRAM Sense Amplifier 1461_bti_analysis_for_high_performance_and_low_power_sram_sense.pdf (March 2015), 4th Workshop On Manufacturable and Dependable Multicore Architectures (MEDIAN 2015), 13 March 2015, Grenoble, France [Conference Paper]
S. Hamdioui, M. Taouil, N.Z.B. Haron, Testing Open Defects in Memristor-Based Memories 1409_testing_open_defects_in_memristorbased_memories.pdf (January 2015), IEEE Transactions on Computers (TC), volume 64, issue 1 [Journal Paper]
E.J. Marinissen, B de Wachter, K Smith, J Kiesewetter, M. Taouil, S. Hamdioui, Direct Probing on Large-Array Fine-Pitch Micro-Bumps of a Wide-I/O Logic-Memory Interface. (October 2014), International Test Conference (ITC 2014), 21-23 October 2014, Seattle, USA [Conference Proceedings]
I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Impact of BTI on SRAM Sense Amplifier in the Presence of Temperature and Process Variation 1453_impact_of_bti_on_sram_sense_amplifier_in_the_presence_of_te.pdf (September 2014), Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands [Conference Proceedings]
M. Taouil, Yield and Cost Analysis for 3D Stacked ICs (September 2014), , (Cum Laude) [Phd Thesis]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Quality versus Cost Analysis for 3D Stacked ICs (April 2014), 32nd IEEE VLSI Test Symposium (VTS 2014), 13-17 April 2014, Napa, USA [Conference Proceedings]
M. Taouil, M. Masadeh, S. Hamdioui, E.J. Marinissen, Interconnect Test for 3D Stacked Memory-on-Logic (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Impact of Mid-Bond Testing in 3D Stacked ICs 1389_impact_of_midbond_testing_in_3d_stacked_ics.pdf (October 2013), 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Using 3D-COSTAR for 2.5D Test Cost Optimization 1388_using_3dcostar_for_25d_test_cost_optimization.pdf (October 2013), IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA [Conference Paper]
M. Lefter, G.R. Voicu, M. Taouil, M. Enachescu, S. Hamdioui, S.D. Cotofana, Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? 1328_is_tsvbased_3d_integration_suitable_for_interdie_memory_r.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
M. Taouil, M. Lefter, S. Hamdioui, Exploring Test Opportunities for Memory and Interconnects in 3D ICs 1337_exploring_test_opportunities_for_memory_and__interconnects.pdf (December 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Paper]
M.S. Khan, S. Hamdioui, M. Taouil, H. Kukner, P. Raghavan, F. Catthoor, Impact of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder Reliablity 1338_impact_of_partial_resistive_defects_and_bias_temperature_in.pdf (December 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Proceedings]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, 3D-COSTAR: A Cost Model For 3D Stacked ICs 1339_3dcostar_a_cost_model_for_3d_stacked_ics.pdf (November 2012), Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012), 8-9 November 2012, Anaheim, USA [Conference Proceedings]
M. Taouil, S. Hamdioui, Yield Improvement for 3D Wafer-to-Wafer Stacked Memories 1341_yield_improvement_for_3d_wafertowafer_stacked_memories.pdf (August 2012), Journal of Electronic Testing: Theory and Applications (JETTA), volume 28 , issue 4 [Journal Paper]
M. Taouil, S. Hamdioui, On Optimizing Test Cost for Wafer-to-Wafer 3D Stacked ICs 1296_on_optimizing_test_cost_for_wafertowafer_3d_stacked_ics.pdf (May 2012), 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 16-18 May 2012, Tunis, Tunisia [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, On Modeling and Optimizing Cost in 3D Stacked-ICs (December 2011), IEEE 6th International Design and Test Workshop (IDT 2011), 11-14 December 2011, Beirut, Lebanon [Conference Paper]
M. Taouil, S. Hamdioui, C.I.M. Beenakker, E.J. Marinissen, Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost 92_test_impact_on_the_overall_dietowafer_3d_stacked_ic_cost.pdf (December 2011), Journal of Electronic Testing: Theory and Applications (JETTA), volume 28, issue 1 [Journal Paper]
S. Hamdioui, M. Taouil, Yield Improvement and Test Cost Optimization for 3D Stacked ICs (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Modeling for 3D-Stacked ICs (September 2011), Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 22-23 September 2011, Anaheim, USA [Conference Paper]
M. Taouil, S. Hamdioui, Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]
M. Taouil, S. Hamdioui, Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs? (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking 227_test_cost_analysis_for_3d_dietowafer_stacking.pdf (December 2010), 19th IEEE Asian Test Symposium (ATS 2010), 1-4 December 2010, Shanghai, China [Conference Paper]
L. Hasan, Z. Al-Ars, M. Taouil, K.L.M. Bertels, Performance and Bandwidth Optimization for Biological Sequence Alignment 236_performance_and_bandwidth_optimization_for_biological_sequen.pdf (December 2010), 5th IEEE International Design and Test Workshop (IDT 2010), 14-15 December 2010, Abu Dhabi, UAE [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking 252_impact_of_test_flows_on_the_cost_in_3d_dietowafer_stacking.pdf (November 2010), First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test), 4-5 November 2010, Austin, USA [Conference Paper]
M. Taouil, S. Hamdioui, J. Verbree, E.J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs 249_on_maximizing_the_compound_yield_for_3d_wafertowafer_stack.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
L. Hasan, Z. Al-Ars, M. Taouil, High Performance and Resource Efficient Biological Sequence Alignment 151_high_performance_and_resource_efficient_biological_sequence.pdf (September 2010), 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2010), 31 August - 4 September 2010, Buenos Aires, Argentina [Conference Paper]
C. van der Bok, M. Taouil, P. Afratis, I. Sourdis, The TU Delft Sudoku Solver on FPGA 374_the_tu_delft_sudoku_solver_on_fpga.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia , 2nd prize FPT-2009 Design Competition Award [Conference Paper]
G.K. Kuzmanov, M. Taouil, Reconfigurable Sparse/Dense Matrix-Vector Multiplier 367_reconfigurable_sparsedense_matrixvector_multiplier.PDF (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]