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J.Y. Hur

NameJ.Y. Hur
First NameJae
E-mail
Author TypePhd Student
AffiliationTU Delft

Publications

J.Y. Hur, K.G.W. Goossens, L. Mhamdi, M.A. Wahlah, Comparative Analysis of Soft and Hard On-Chip Interconnects for FPGAs 1334_comparative_analysis_of_soft_and_hard_onchip_interconnects.pdf (December 2012), IET Computers & Digital Techniques (CDT), volume 6, issue 1 [Journal Paper]
J.Y. Hur, T.P. Stefanov, S. Wong, K.G.W. Goossens, Customisation of on-chip network interconnects and experiments in field-programmable gate arrays 124_customisation_of_onchip_network_interconnects_and_experimen.pdf (January 2012), IET Computers & Digital Techniques (CDT), volume 6, issue 1 [Journal Paper]
J.Y. Hur, Customizing and Hardwiring On-Chip Interconnects in FPGAs 90_customizing_and_hardwiring_onchip_interconnects_in_fpgas.pdf (February 2011), [Phd Thesis]
T. Marconi, J.Y. Hur, K.L.M. Bertels, G.N. Gaydadjiev, A Novel Configuration Circuit Architecture to Speedup Reconfiguration and Relocation for Partially Reconfigurable Devices 179_a_novel_configuration_circuit_architecture_to_speedup_reconf.pdf (June 2010), IEEE 8th Symposium on Application Specific Processors (SASP 2010), 13-14 June 2010, Anaheim, USA [Conference Paper]
J.Y. Hur, K.G.W. Goossens, L. Mhamdi, Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit-Switched Interconnects for FPGAs 541_performance_analysis_of_soft_and_hard_singlehop_and_multih.pdf (October 2008), 16th International Conference on Very Large Scale Integration (VLSI-SoC 2008), 13-15 October 2008, Rhodes Island, Greece [Conference Paper]
J.Y. Hur, S. Wong, T.P. Stefanov, Design Trade-offs in Customized On-chip Crossbar Schedulers 429_design_tradeoffs_in_customized_onchip_crossbar_schedulers.pdf (September 2008), Journal of Signal Processing Systems (JSPS) [Journal Paper]
J.Y. Hur, S. Wong, S. Vassiliadis, Partially reconfigurable point-to-point FPGA interconnects 461_partially_reconfigurable_pointtopoint_fpga_interconnects.pdf (July 2008), International Journal of Electronics (IJE), volume 95, issue 7 , Special Issue: Reconfigurable Hardware Systems [Journal Paper]
K.G.W. Goossens, M. Bennebroek, J.Y. Hur, M.A. Wahlah, Hardwired Networks on Chip in FPGAs to unify Data and Configuration Interconnects 488_hardwired_networks_on_chip_in_fpgas_to_unify_data_and_config.pdf (April 2008), 2nd International Symposium on Networks-on-Chips (NOCS 2008), 5-6 April 2008, Newcastle, UK [Conference Paper]
A. Shahbahrami, J.Y. Hur, B.H.H. Juurlink, S. Wong, FPGA Implementation of Parallel Histogram Computation 555_fpga_implementation_of_parallel_histogram_computation.pdf (January 2008), 2nd HiPEAC Workshop on Reconfigurable Computing (WRC 2008), 27 January 2008, Göteborg, Sweden [Conference Paper]
J.Y. Hur, T.P. Stefanov, S. Wong, S. Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler 594_customizing_reconfigurable_onchip_crossbar_scheduler.pdf (July 2007), 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2007), 8-11 July 2007, Montréal, Canada [Conference Paper]
J.Y. Hur, S. Wong, S. Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs 633_partially_reconfigurable_pointtopoint_interconnects_in_vir.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
J.Y. Hur, T.P. Stefanov, S. Wong, S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects 632_systematic_customization_of_onchip_crossbar_interconnects.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
S. Wong, S. Vassiliadis, J.Y. Hur, Parallel Merge Sort on a Binary Tree On-Chip Network 878_parallel_merge_sort_on_a_binary_tree_onchip_network.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]