J.Y. Hur, T.P. Stefanov, S. Wong, K.G.W. Goossens, Customisation of on-chip network interconnects and experiments in field-programmable gate arrays (January 2012), IET Computers & Digital Techniques (CDT), volume 6, issue 1 [Journal Paper]

R. Nane, S. van Haastregt, T.P. Stefanov, B. Kienhuis, V.M. Sima, K.L.M. Bertels, IP-XACT Extensions for Reconfigurable Computing (September 2011), 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), 11-14 September 2011, Santa Monica, USA [Conference Paper]

R. Nane, S. van Haastregt, T.P. Stefanov, B. Kienhuis, K.L.M. Bertels, An HdS Meta-Model Case Study: Integrating Orthogonal Computation Models (March 2011), Workshop DATE 2011 : Hardware Dependent Software (HdS) Solutions for SoC Design (DATE 2011 Workshop), 18 March 2011, Grenoble, France [Conference Paper]

Z. Nawaz, T.P. Stefanov, K.L.M. Bertels, Efficient hardware generation for dynamic programming problems (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]

O.S. Dragomir, T.P. Stefanov, K.L.M. Bertels, Optimal Loop Unrolling and Shifting for Reconfigurable Architectures (September 2009), ACM Transactions on Reconfigurable Technology and Systems (TRETS), volume 2, issue 4 [Journal Paper]

Z. Nawaz, T. Marconi, T.P. Stefanov, K.L.M. Bertels, Optimal pipeline design for Recursive Variable Expansion (July 2009), 5th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2009), 12-18 July 2009, Terrassa, Spain [Conference Paper]

Z. Nawaz, T. Marconi, T.P. Stefanov, K.L.M. Bertels, Flexible Pipelining Design for Recursive Variable Expansion (May 2009), 23rd IEEE International Symposium on Parallel and Distributed Processing (IPDPS 2009), 23-29 May 2009, Rome, Italy [Conference Paper]

O.S. Dragomir, T.P. Stefanov, K.L.M. Bertels, Loop Unrolling and Shifting for Reconfigurable Architectures (September 2008), 18th International Conference on Field Programmable Logic and Applications (FPL 2008), 8-10 September 2008, Heidelberg, Germany [Conference Paper]

J.Y. Hur, S. Wong, T.P. Stefanov, Design Trade-offs in Customized On-chip Crossbar Schedulers (September 2008), Journal of Signal Processing Systems (JSPS) [Journal Paper]

O.S. Dragomir, T.P. Stefanov, K.L.M. Bertels, Loop Optimizations for Reconfigurable Architectures (July 2008), 4th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2008), 13-19 July 2008, L'Aquila, Italy , ACACES Poster Abstracts [Conference Paper]

M. Azkarate-Askasua, T.P. Stefanov, JPEG2000 Image Compression in Multi-Processor System-on-Chip (July 2008), CE technical report [Technical Report]

K. Sigdel, M. Thompson, A.D. Pimentel, T.P. Stefanov, K.L.M. Bertels, System-Level Design Space Exploration of Dynamic Reconfigurable Architectures (July 2008), 8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2008), 21-24 July 2008, Samos, Greece [Conference Paper]

E. Cannella, T.P. Stefanov, G.N. Gaydadjiev, Performance Evaluation of Multi-threading Operating Systems in MPSoCs generated by ESPAM (June 2008), CE technical report [Technical Report]

J.Y. Hur, T.P. Stefanov, S. Wong, S. Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler (July 2007), 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2007), 8-11 July 2007, Montréal, Canada [Conference Paper]

J.Y. Hur, T.P. Stefanov, S. Wong, S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]